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Volume 12, Issue 02

Intel's 45nm CMOS Technology


Intel Technology Journal - Featuring Intel's recent research and development

ISSN 1535-864X DOI 10.1535/itj.1202.05

  • Volume 12
  • Issue 02
  • Published June 17, 2008

Intel's 45nm CMOS Technology

  Section 2 of 12  

45nm Design for Manufacturing

INTRODUCTION

The difficulties in continuing Moore's Law with the lack of improvement in lithography resolution are well known [1, 2, 3]. Design rules have to change and Design for Manufacturing (DFM) methodology has to continue to improve to enable Moore's Law scaling. In this paper we discuss our approach to DFM through co-optimization across design and process. We define the design rules for a new technology early in the definition process well before the technology development is complete. This early definition of design rules allows the design to start in parallel with the technology development. Early accurate modeling of the design rules and layout is a key to making this process successful. The design rules must meet the requirements of a highly manufacturable process at the beginning of the production ramp for the first product.

Our DFM goals and methodology are different from those of some other manufacturers. The basic rules for drawing transistors, other layers, and DFM requirements are not separate in our definition process. We have a few guidelines such as suggesting that designers use redundant vias where possible, but most of our DFM requirements are included as required rules that all designs must meet for all layout. Some other companies have simple basic layout rules and provide other rules that are guidelines or suggestions for changes to layout or design that would improve manufacturability or reduce variation. Designers make tradeoffs for area and cost to decide if they will implement these guidelines. Some of their DFM changes are available only after analysis of the initial layout. Another difference in our methodology is that we tend toward adding rules to prevent something in layout that might affect design, instead of depending upon modeling of product layout to find problems. We build the requirements for manufacturability and low variation into the basic design rules as hard design rule requirements. Product design starts in parallel with technology development. Design rules must not be changed significantly after design work starts. Our DFM methodology depends upon modeling to define the rules very early in technology development. Therefore, our methodology ensures that products are ready for ramp-up in multiple fabs to high-volume and high-yield manufacturing without changes. This may make our design rules more complicated than those of some of our competitors, but this methodology ensures that all our products are capable of high yield when they tape in their first stepping.

Co-optimization across process and design is required to ensure we understand and balance all requirements. By co-optimizing design and process early in the development cycle, we arrived at a set of design rules that met 45nm process and design requirements. The thoroughness of this early work resulted in these rules being stable through the development cycle, which led to the successful insertion of 45nm technology in high-volume manufacturing, ensuring the continued march of Moore's Law.

The poly layer is the most critical layer for control of variation. Due to this need to control variation, the poly layer was the first layer on which restrictive design rules were used. We need to build the requirements for minimizing variation into the rules. How the rules have changed for the poly layer shows how designs have changed. The analysis of the impact of changes in the poly rule shows how we consider design and process needs in defining design rules.

  Section 2 of 12  

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