Intel's 45nm CMOS Technology

45nm Design for Manufacturing

REFERENCES

[1] G.E. Moore, "Lithography and the Future of Moore's Law." In Proceedings SPIE, vol. 2440, 1995, pp. 2–17.

[2] Borodovsky, Yan, "Marching to the Beat of Moore’s Law." In Proceedings SPIE, vol. 6153, Advances in Resist Technology and Processing XXIII, March 2006.

[3] Alfred K. Wong, "Microlithography: Trends, Challenges, Solutions, and their Impact on Design." IEEE Micro, vol. 23, no. 2, March/April 2003, pp. 12–21.

[4] Shekhar Borkar, "Parameter Variations and Impact on Circuits and Microarchitecture." 40th Design Automation Conference, 338, (DAC'03), 2003.

[5] Kuhn, Kelin J., "Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale Cmos." IEDM 2007, pp. 471–474.

[6] Mistry, Kaizad A, "45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging." IEDM 2007, pp. 247–250.

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