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Volume 12, Issue 02

Intel's 45nm CMOS Technology


Intel Technology Journal - Featuring Intel's recent research and development

ISSN 1535-864X DOI 10.1535/itj.1202.05

  • Volume 12
  • Issue 02
  • Published June 17, 2008

Intel's 45nm CMOS Technology

Section 1 of 12  

45nm Design for Manufacturing

Clair Webb, Technology and Manufacturing Group, Intel Corporation

Index Words: DFM, 45nm, design rules

Citations for this paper: Webb, C. "45nm Design for Manufacturing." Intel Technology Journal. http://www.intel.com/technology/itj/2008/
v12i2/1-abstract.htm
(June 2008).

ABSTRACT

Co-optimization between design and process is required for a highly manufacturable process technology. This paper discusses this co-optimization and how it meets the challenges for maintaining Moore's Law while delivering new processes and designs capable of fast ramp to high yields. Poly is one of the most critical layers for control of variation, and it needs the most restrictive rules. We show the change in poly rules over the last few processes to illustrate how rules have changed to meet manufacturing requirements. The variation, density, and yields on the 45nm process show the success of this Design for Manufacturing (DFM) methodology.

Section 1 of 12  

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