Intel's 45nm CMOS Technology

45nm SRAM Technology Development and Technology Lead Vehicle

AUTHORS’ BIOGRAPHIES

Uddalak Bhattacharya
Uddalak Bhattacharya is a Principal Engineer in the Logic Technology Development Organization at Intel Corporation. His interests include SRAM test circuit design, testing, measurement, and yield analysis. He received his Ph.D. degree in Electrical Engineering from the University of California, Santa Barbara in 1996. His e-mail is uddalak.bhattacharya at intel.com.

Yih Wang
Yih Wang is a Senior Design Engineer in Intel's Logic Technology Development Organization. He joined Intel in 2001 after receiving his Ph.D. degree from the University of Florida. He has worked on SRAM developments for a variety of Intel logic process technologies. Currently, he is responsible for developing the low-power and high-speed SRAM designs for future logic processes. His e-mail is yih.wang at intel.com.

Fatih Hamzaoglu
Fatih Hamzaoglu received his Ph.D. degree from the University of Virginia, Charlottesville, in 2002, in Electrical Engineering. After his Ph.D., he joined the Logic Technology Development Group at Intel Corporation. Since then, he has been working on low-power, high-performance SRAM cache design. He is the author/co-author of 19 papers and holds four issued and 6 pending patents. His e-mail is fatih.hamzaoglu at intel.com.

Yong-Gee Ng
Yong-Gee Ng is a Senior Design Engineer at the Portland Technology Development Group. His interests are in low-power, high-performance SRAM cache designs. He received B.A. and M.S. degrees in Electrical Engineering from Arizona State University, Tempe, in 1989 and 1991, respectively. His e-mail is yong-gee.ng at intel.com.

Liqiong Wei
Liqiong Wei is a Component Design Engineer in the Logic Technology Development Group at Intel. Her technical interests include low-power, high-performance memory design and validation. She received her B.S. and M.S. degrees in Electrical Engineering from Peking University, Beijing, and a Ph.D. degree in Electrical and Computer Engineering from Purdue University. She is a member of the IEEE. Her e-mail is liqiong.wei at intel.com.

Zhanping Chen
Zhanping Chen received a B.S. degree in Computer Science and Technology from Peking University, Beijing, China, and a Ph.D. degree in Electrical and Computer Engineering from Purdue University, West Lafayette, IN, in 1991 and 1999, respectively. He joined Intel Corporation in June 1999 and currently leads the development of programmable read-only memory (PROM). His research interests include CAD tool development and circuit design/optimization for low power and high performance. Dr. Chen received the Best Paper Award at the 2000 IEEE International Symposium on Quality Electronic Design, San Jose, CA. His e-mail is zhanping.chen at intel.com.

Joe Rohlman
Joe Rohlman is an Engineering Manager in the Advanced Design Group in the Logic Technology Development Organization. He leads a team of engineers focused on mixed signal circuit design on Intel's next-generation process technology. Prior to joining the Logic Technology Development Organization, Joe held management and design roles on Microprocessor and Ethernet product teams. Joe received an MSEE degree from the University of Michigan. His e-mail is joseph.f.rohlman at intel.com.

Ian Young
Ian Young is a Senior Fellow and Director of Advanced Circuits and Technology Integration in the Technology and Manufacturing Group at Intel. He received his B.A. and M.S. degrees in Electrical Engineering from the University of Melbourne, Australia. He received his Ph.D. in Electrical Engineering from the University of California, Berkeley. He is currently directing the development of high-speed serial I/O and mixed-signal analog circuits in 32nm logic and SOC technologies and doing research for optical I/O. His e-mail is ian.young at intel.com.

Kevin Zhang
Kevin Zhang is an Intel Fellow and Director of Advanced Memory Circuits and Technology Integration in the Logic Technology Development Group at Intel Corporation. He is responsible for embedded memory technology development and has led the design and validation of technology vehicles from 90nm to 45nm technology generations, which played a key role in both process technology development and product design. He holds a Ph.D. degree in Electrical Engineering from Duke University. His e-mail is kevin.zhang at intel.com.

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