Intel's 45nm CMOS Technology

45nm SRAM Technology Development and Technology Lead Vehicle

REFERENCES

[1] W. Chen and U. Bhattacharya, "Method for bi-directional data synchronization between different clock frequencies." US Patent 6,956,918.

[2] M. Hatizalambrou, A. Neureuther, and C. Spanos, "Ring oscillator sensitivity to spatial process variation." 1st International workshop on Statistical Metrology (IWSM), June 1996.

[3] K. Mistry, et al., "A 45nm Logic Technology with higk-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging." IEDM Technical Digest, December 2007, pp. 247–250.

[4] K.-S. Min, K. Kanda, and T. Sakurai, "Row-by-row dynamic source-line voltage control (RRDSV) scheme for two orders of magnitude leakage current reduction of sub-1-V-VDD SRAM’s." In Proceedings IEEE International Symposium Low Power Electronics and Design (ISLPED), August 2003, pp. 66–71.

[5] K. Zhang, et al., "SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction." IEEE J. Solid-State Circuits, vol. 40, April 2005, pp. 895–901.

[6] M. Khellah, et al., "A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process with Actively Clamped Sleep Transistor." IEEE J. Solid-State Circuits, vol.42, January 2007, pp. 233–242.

[7] V. George, et al., "Penryn: 45-nm Next Generation Intel® Core™2 Processor." ASSCC Technical Digest, November 2007, pp. 14–17.

[8] F. Hamzaoglu, et al.,"A 153Mb-SRAM design with dynamic stability enhancement and leakage reduction in 45nm High-K Metal-Gate CMOS technology." ISSCC Technical Digest, June 2008, pp. 376–377.

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