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Volume 12, Issue 02

Intel's 45nm CMOS Technology


Intel Technology Journal - Featuring Intel's recent research and development

ISSN 1535-864X DOI 10.1535/itj.1202.04

  • Volume 12
  • Issue 02
  • Published June 17, 2008

Intel's 45nm CMOS Technology

  Section 5 of 8  

45nm SRAM Technology Development and Technology Lead Vehicle

SUMMARY

The role of the X6 testchip in the 45nm Hi-K metal gate process development is discussed in this paper. X6 played a critical role in supporting process development by providing a platform for process yield and performance enhancement. In parallel it also served as a test bed for co-optimization of critical design collaterals with the process technology. There exists a significant advantage in having the process technology and the critical design collaterals ready simultaneously for product use. Design considerations and performance of some of the collaterals such as the SRAM memory bit and subarray, PLL, DTS, and high-speed I/Os has been outlined. The early effort on X6 was a key contributor to the success of the lead product ramp in the 45nm Hi-K metal gate technology.

  Section 5 of 8  

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