Intel's 45nm CMOS Technology

45nm SRAM Technology Development and Technology Lead Vehicle

X6 FUSE

Fuse-based electrically programmable read-only memories (PROM) have been widely used in microprocessors for a variety of important applications. These include improving microprocessor yield by repairing defective SRAM bits using row/column redundancy, permanently storing die identification, and effectively trimming devices used in analog circuits such as thermal sensors and I/O. Fuse designs in X6 were optimized for the Hi-K metal gate process. In this generation we developed an array-based design for high-density fuses that significantly improved the area efficiency of the fuse block for increased product applications.

X6 Mixed Signals and Analog Circuits

The X6 technology lead vehicle includes a group of mixed signal and analog collateral circuits. CPU products require increasing amounts of analog circuit content. The analog technology dependencies differ from digital dependencies by device and component type, and they have a stronger focus on gain and operating range metrics as opposed to digital drive current and capacitive load. A technology that produces high-yielding, high-performing SRAM and digital logic does not ensure analog circuit functionality and performance. Including analog circuits on the X6 technology lead vehicle enabled evaluation of unique analog technology requirements.

A set of circuits targeted at the lead 45nm product were incorporated in the design to allow greater technology flexibility. They include PLL, Gunning Transceiver Logic (GTL) I/O buffers, and DTS. The PLL design also includes multiple types of Voltage Controlled Oscillators (VCO) for design optimization. The GTL I/O buffer contains programmable termination resistors for design tuning. All these circuits have been directly used in the lead product design. Figure 9 shows a waveform captured from the product I/O.

Figure 9: GTL I/O waveform (X-axis 1ns/div)
click image for larger view
 

As CPUs demands more data bandwidth, the future generation of Intel CPUs will feature new high-speed serial I/Os, also called Quick Path Interconnect (QPI) circuits. Many circuits used in the physical implementation of QPI circuits have strong process technology dependency. Several critical components of QPI circuits, including differential transceiver, Delay Locked Loop (DLL), duty cycle correction circuits, and low-jitter LC-PLL are incorporated in X6 and provide significant early silicon-based learning. A capability of 6.4GT/s has been demonstrated as shown by the eye-diagram in Figure 10.

Figure 10: 6.4GT/s operation shows clean eye-diagram and error-free with BIST
click image for larger view
 

Back to Top