Intel's 45nm CMOS Technology

45nm SRAM Technology Development and Technology Lead Vehicle

INTRODUCTION

"X-chips" have been serving the needs of process technology development at Intel for many generations. They have always been based on SRAM building blocks. SRAM has the unique advantages of stressing the most critical design rules of a process technology, providing large area coverage that increases defect sensitivity, and of providing fine addressable granularity to enable fault isolation and analysis.

In this paper we focus on X6, the testchip that was used to certify the Hi-K metal gate process technology at the 45nm node. Over the generations, the X-chips have evolved beyond the original goal of providing test data needed to identify process defects, to a platform for the co-optimization of process technology and critical design collaterals for the products. In the following section, we provide an overview of the X-chip.

Testability is a key concern with X-chips, and X6 is no exception. The testchip must be sensitive to process defects and must exercise the critical design rules. A process should not get certified on the testchip and encounter yield or performance issues when a product is subsequently ramped on it. The complexity of modern semiconductor processes results in significant lead time from wafer starts to end of line, while the total time available to certify a process remains, at best, the same. For the process engineer this means only a limited number of "info-turns" during the development phase. To reduce this information turnaround time, X6 includes a test infrastructure that allows the collection of relevant data with reduced test time and features that aid fault isolation. We discuss this aspect further in the test features section.

We now provide descriptions of the critical design collateral content of X6 SRAMs and some key mixed-signal circuits that have high process sensitivities in the context of product design. Therefore, these classes of circuits are obvious choices to be included in the testchip. We discuss a product-ready and tileable common SRAM subarray design along with performance results. In addition to 6T SRAM arrays, X6 also included multi-port SRAM, a.k.a., register file (RF) memories, for the first time to broaden the process and product co-learning. New fuse technology is developed with X6 to provide for expanded product requirements. A significant number of analog elements such as different kinds of Phase Lock Loop (PLL), Digital Thermal Sensors (DTS), and advanced I/O circuits were also part of the X6 testchip. In the following sections these collaterals are described along with the key learnings for technology development and circuit optimization.

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