Intel's 45nm CMOS Technology

Managing Process Variation in Intel's 45nm CMOS Technology

AUTHORS’ BIOGRAPHIES

Kelin J. Kuhn
Kelin J. Kuhn is an Intel Fellow in the Technology and Manufacturing Group and Director of Logic Device Technology. Dr. Kuhn received a B.S. degree in Electrical Engineering from the University of Washington in 1980, and M.S. and Ph.D. degrees in Electrical Engineering from Stanford University in 1985. Dr. Kuhn is presently the device lead of the pathfinding team responsible for the transistor architecture for Intel's 22nm process technology and was the device lead for Intel's 45nm process. She joined Intel Corporation in 1997, and since then she has held a variety of technical positions on the 0.35um, 130nm, and 90nm nodes. Previously, Kuhn was a tenured faculty member in the Department of Electrical and Computer Engineering at the University of Washington. Dr. Kuhn is the author of numerous technical publications on the optical and electronic properties of semiconductor devices as well as the author of the textbook Laser Engineering. She received the 2006 Intel Achievement award for her work in enabling Intel's 45nm node High-k metal gate transistor process. Her e-mail is kelin.ptd.kuhn at intel.com.

Chris Kenyon
Chris Kenyon is a lithography group leader in Intel's Logic Technology Development organization. He joined Intel in 1996 and has worked primarily on Intel's gate-patterning process since that time. He is currently responsible for developing the gate-patterning process for the 32 and 22nm nodes. He received his B.A. degree from Princeton University in 1990 and his Ph.D. degree from Caltech in 1996 in Physical Chemistry. His e-mail is Chris.Kenyon at intel.com.

Avner Kornfeld
Avner Kornfeld is a Principal Engineer in the Technology and Manufacturing Group working on analog design, variation, and on the interaction between design and process. Prior to his current role he worked on power and frequency optimization and projection for Intel mobile microprocessors in 130nm, 90nm, 65nm, and 45nm nodes. He joined Intel in 1992 and worked for the Intel Communication and the Mobile Microprocessor Groups. He received B.Sc., M.Sc., and D.Sc. degrees in Electrical Engineering from the Technion–Israel Institute of Technology in 1980, 1982, and 1986, respectively. Dr. Kornfeld was a lecturer in the Department of Electrical Engineering–Technion, from 1986 to 1991 working on cryogenic focal plane signal processing and device flicker noise. He received the 1997 Intel Achievement Award for his work on Intel's 100/10 Mbps fast Ethernet transceiver design. His e-mail is avner.kornfeld at intel.com.

Mark Y. Liu
Mark Y. Liu is a Process Integration Engineer in Intel's Logic Technology Development organization. He joined Intel in 1995 as a Process Engineer in the ion implantation group and later held positions as Ion Implantation Group Leader and Advanced Thermal Annealing Group Leader. He received his Ph.D. degree in Electrical Engineering from the University of Minnesota and his B.S. degree in Physics from Beijing University in China. His e-mail is mark.y.liu at intel.com.

Atul Maheshwari
Atul Maheshwari is a Senior Design Engineer in the Logic Technology Development Department of the Technology and Manufacturing Group. He is responsible for the delivery of performance and process variation probing circuits for 45nm and 32nm process technology. He received his B.E degree from Gujarat University, India in 1998 and M.S. and Ph.D. degrees in Electrical and Computer Engineering from the University of Massachusetts, Amherst in 2001 and 2004, respectively. His e-mail is atul.maheshwari at intel.com.

Wei-Kai Shih
Wei-Kai Shih received a Ph.D. degree in Electrical Engineering from the University of Texas at Austin in 1997, with a focus on device physics and TCAD simulation. He joined Intel TCAD in 1997 to develop a full-chip thermal reliability methodology and related simulation tools, which later became part of RV-TPRSIM. He has also worked extensively in the area of compact transistor modeling, specifically gate leakage modeling and analog-RF modeling. Wei-kai Shih is currently a Group Lead in the DTS Core CAD Technology Department, managing a group of 15 CAD developers to deliver interconnect, process variation, and reliability models and simulation tools, as well as their application to technology and design co-optimization.

Sam Sivakumar
Sam Sivakumar is an Intel Fellow and Director of Lithography in Intel's Portland Technology Development Group in Oregon. He is responsible for the definition, development, and deployment of Intel's next-generation lithography processes. Sivakumar joined Intel in 1990 and throughout his career with the company has worked in the lithography area on photoresists, patterning equipment, and process development. He has contributed to lithography development, characterization, and transfer to high-volume manufacturing of every submicron process technology generation at Intel since 1990.

Greg Taylor
Greg Taylor is an Intel Fellow in the Technology and Manufacturing Group and Director of Mixed Signal Circuit Technology. He is responsible for the delivery of the analog circuits needed by future microprocessors. Prior to his current role he worked on the development of eight generations of Intel microprocessors since joining the company in 1991, with a focus on the mixed signal portions of these chips. Before joining Intel, Dr. Taylor worked at Bipolar Integrated Technology where he worked on ECL floating point units and two RISC microprocessors. He received the B.S., M.S., and D.Eng. degrees in Computer and Systems Engineering from Rensselaer Polytechnic Institute in 1981, 1983, and 1985, respectively, where he was supported by a Fannie and John Hertz Foundation Fellowship. His e-mail is greg.design.taylor at intel.com.

Peter VanDerVoorn
Peter VanDerVoorn is a Device Engineer in the Technology and Manufacturing Group. Dr. VanDerVoorn received the B.S. and Ph.D. degrees in Electrical Engineering from Cornell University in 1992 and 1998. He is presently the Device Engineer responsible for 45nm process enhancement and has been involved in the 45nm High-K/metal gate program from the pathfinding phase. Dr. VanDerVoorn joined Intel Corporation in 1998 and has since held Process Integration and Device Engineering positions in the 130nm, 90nm, and 45nm nodes. His e-mail is peter.j.VanDerVoorn at intel.com.

Keith Zawadzki
Keith Zawadzki is a Device Engineer in Intel's Logic Technology Development organization. He joined Intel in 1998 and is currently responsible for developing 22nm process technology. He received a B.Sc. degree in Microelectronic Engineering from the Rochester Institute of Technology in 1996 and an EEMS degree from the University of Texas, Austin in 1998. His e-mail is Keith.E.Zawadzki at intel.com.

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