Intel's 45nm CMOS Technology

  Section 6 of 9  

Managing Process Variation in Intel's 45nm CMOS Technology

CONCLUSION

Although there has been a trend in the CMOS literature in recent years to convey process variation as a new challenge, process variation has always been a critical element in semiconductor fabrication. From the first discussion of random variation by Shockley in 1961 [3] to the most recent 45nm results [14, 17], understanding and mitigating process variation has been a continuing theme throughout semiconductor history.

While management of process variation is likely to play an increasingly important role in technology scaling, a variety of process, design, and layout techniques can be applied to mitigate the impact of this variation. Examples of pure process mitigation techniques used in the 45nm technology include targeting key transistor properties to reduce RDF, reducing traps at the HiK+MG interface to reduce random charge variation, improving patterning techniques to reduce LER and endcap variation, and improving polishing technologies to reduce systematic cross-wafer variation. Examples of combination design-process techniques used in the 45nm generation include optimizing topology, using OPC to reduce random and systematic variation and adding dummy features to reduce systematic variation. Examples of pure design techniques used in the 45nm generation include chopping techniques to compensate for random variation and common-centroid techniques to compensate for systematic variation.

The success of the 45nm process variation mitigation techniques is well illustrated by 45nm data. In-line measurements of gate CD across four generations show that the 45nm technology generation was able to maintain a 0.7X scaling to prior generations for WID, WIW, and total variation. Intrinsic random variation extracted from matched transistor pairs shows an ~20% improvement in intrinsic random variation from the 65nm to 45nm generations. Systematic WIW variation data from ring oscillators on microprocessor product material illustrates that systematic variation has remained essentially constant across the last four generations. Random WIW variation data from ring oscillators on microprocessor product material illustrates an ~50% improvement in random variation between the 65nm and 45nm generations enabled by HiK+MG. Ring oscillator data (used in conjunction with a calibration structure) shows that NMOS average systematic WID V_T variation has improved 45% (from 20mV to 11mV) and PMOS has improved 22% (from 9mV to 7mV) between the 65nm and 45nm generations.

The key message of this paper is that process variation is not an insurmountable barrier to Moore's Law, but is simply another challenge to be overcome. This message is illustrated with data from the 45nm process generation where process variation is shown to be at least equivalent to (and in many cases better than) process variation in the 65nm and 90nm process generations.

  Section 6 of 9  

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