Intel's 45nm CMOS Technology

Managing Process Variation in Intel's 45nm CMOS Technology

CHARACTERIZATION OF VARIATION IN THE 45NM GENERATION

We illustrate the success of these mitigation techniques by reviewing detailed data characterizing variation in the 45nm generation. Three different types of measurements are presented to illustrate various variation mechanisms. The first is an in-fab measurement of variation, used to characterize CD variation for 45nm versus 65nm and 90nm generations. The second is DC electrical measurement of matched transistor pairs, used to extract random variation for 45nm versus 65nm transistors. The third is frequency measurements of product ring oscillators, used to determine both systematic and random WIW and within-die (WID) variation for 45nm versus 65nm products.

In-Fab Characterization of Critical Dimension (CD)

Maintaining poly-gate control is critical for managing variation between process generations. Figure 19 presents summary data from in-line measurements of gate CD across four generations that show that the 45nm technology generation was able to maintain a 0.7X scaling to prior generations for WID, WIW, and total variation.

Figure 19: The 45nm generation continued the historical scaling trend of 0.7X in poly-gate variation control
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DC Measurement of Matched Transistor Pairs

DC electrical measurement of matched transistor pairs is a basic technique used to extract random variation for 45nm versus 65nm transistors. Figure 20 illustrates the random variation for both 65nm and 45nm generations as extracted from matched transistor pairs. Note an ~20% improvement in intrinsic random variation from the 65nm to 45nm generations.

Figure 20: Pelgrom plot illustrating the improvement of the 45nm over 65nm generations
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Ring Oscillator Measurements

A powerful tool for assessing process variation is locating ring oscillators (see Figures 21 and 22) routinely in all product designs. The detailed ring-oscillator data can be used to identify areas of concern for process teams to resolve.

Figure 21: Ring oscillators can be located in product die
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Figure 22: Ring oscillators were added to 45nm products to provide detailed within-die and within-wafer variation data on revenue product material
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Figures 23 and 24 show examples of the use of ring-oscillator frequency to determine systematic and random WIW variation across generations. Systematic WIW variation data from ring oscillators (Figure 23) on microprocessor product material illustrates that systematic variation has remained essentially constant across the last four generations. Random WIW variation data from ring oscillators (Figure 24) on microprocessor product material illustrates the ~50% improvement in random variation between the 65nm and 45nm generations enabled by HiK+MG. Note also that the 45nm random WIW variation is comparable to the 130nm process generation.

Figure 23: Systematic within-wafer variation data from ring oscillators on microprocessor product material illustrating that systematic variation has remained constant across the last four generations
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Figure 24: Random within-wafer variation data from ring oscillators on microprocessor product material illustrating the ~50% improvement in random variation enabled by HiK+MG between the 65nm and 45nm generations
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Figure 25 gives an example of ring-oscillator data (used in conjunction with a calibration structure) to extract average systematic WID V_T variation comparisons between 65nm and 45nm generations. Note that NMOS has improved 45% (from 20mV to 11mV) and PMOS has improved 22% (from 9mV to 7mV) between the 65nm and 45nm generations.

Figure 25: Ring-oscillator data (used in conjunction with a calibration structure) to extract 65nm to 45nm systematic within-die NMOS and PMOS V_T variation illustrating the improvement is enabled by HiK+MG between the 65nm and 45nm generations
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