Intel's 45nm CMOS Technology

Managing Process Variation in Intel's 45nm CMOS Technology

PROCESS, DESIGN AND LAYOUT TECHNIQUES USED IN THE 45NM GENERATION TO MITIGATE THE IMPACT OF VARIATION

Many techniques were applied in the 45nm generation to mitigate the impact of process variation. These techniques can be characterized as pure process techniques (i.e., techniques transparent to design), combination process-design techniques (i.e., techniques that exercise tight cooperation between process and design), and pure design techniques (i.e., techniques transparent to process). Examples of pure process mitigation techniques include targeting key transistor properties to reduce random dopant fluctuation, reducing traps at the HiK+MG interface to reduce random charge variation, improving patterning techniques to reduce LER and endcap variation, and improving polishing technologies to reduce systematic cross-wafer variation. Examples of combination design-process techniques include optimizing topology, using optical proximity correction to reduce random and systematic variation, and adding dummy features to reduce systematic variation. Pure design techniques include chopping and autozeroing to compensate for random variation and common-centroid layout to compensate for systematic variation.

Process Mitigation Techniques

Pure process mitigation techniques are techniques implemented by the process and transparent to design. As an example, recall that RDF is a major contributor to random variation and is frequently represented by Stolk's formulation (Equation 2)

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illustrating that matching improves with decreases in channel doping (N) and gate oxide thickness (Tox), and degrades when device area decreases [12].

Historical scaling (which reduces gate oxide thickness) suggests a continued improvement in the random variation coefficient (C2). However, as illustrated in Figure 8, the historical improvement trend in C2 slowed when gate leakage concerns limited gate oxide scaling with conventional gate oxides at the 65nm generation. The introduction of 45nm HiK+MG, which restored historical gate oxide scaling due to reduction in gate oxide leakage, was a pure process technique that mitigated the impact of RDF and enabled a return to an historical scaling trend.

Figure 8: HiK+MG enables a return to an historical scaling trend with associated improvement in C2
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Traps in the HiK+MG dielectric are another source of random variation. A number of process improvements were incorporated in the 45nm process to reduce the impact of traps. Figure 9 shows pulsed IV characteristics for early versions of the HiK process vs. a later improved version. Initial HiK+MG material showed a large hysteresis effect—as well as high-bias-temperature instability (BTI) degradation in direct-current (DC) stress. Later versions of the process (incorporating a variety of improvements) showed negligible hysteresis demonstrating that traps were virtually eliminated.

Figure 9: Dielectric trap improvement in the 45nm generation as measured with pulsed IV [64]
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LER and LWR are key contributors to random variation in advanced technologies. A variety of advanced patterning techniques were applied in the 45nm generation to improve the patterning and reduce the LER (see Figure 10).

Figure 10: A variety of techniques were applied in the 45nm generation to improve the patterning and reduce the LER
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Another lithographic variation improvement incorporated in the 45nm generation was to change the poly-patterning process so that the poly endcaps are square rather than rounded (see Figure 11 and 7). Square endcaps eliminate the systematic variation associated with "dogbone" and "icicle" endcaps.

Figure 11: Square poly endcaps implemented in 45nm technology to eliminate the variation of "dogbone" and "icicle" endcaps
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A number of modules in the 45nm generation were able to incorporate significant process improvements to reduce systematic variation. One of many examples is shown in Figure 12, which illustrates the improvement in 45nm MT1 within-wafer (WIW) resistance uniformity over the 65nm generation due to improvements in Cu CMP.

Figure 12: Improvement in 45nm MT1 within-wafer resistance uniformity due to improvements in Cu CMP
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Combination Process—Design Mitigation Techniques

Combination process-design mitigation techniques are techniques that exercise tight cooperation between process and design. An example of a combination process-design mitigation strategy is to change the topology of the SRAM from a "tall" design to a "wide" design (see Figure 7 and Ref. [19]). The wide design improves CD control and variation by aligning the poly in a single direction, eliminating diffusion corners, and relaxing some patterning constraints on other critical layers.

Combination design-process improvements resulting from optimization between reticle enhancement techniques and the lithography process were widely used in the 45nm generation. An example is shown in Figure 13, which shows the improvement resulting from an OPC/RET update that resolved the issue of a poor resist profile causing variation in metal pattern after etch.

Figure 13: An example of a design-process OPC/RET update in the 45nm generation that resolved the issue of a poor resist profile causing variation in metal pattern after etch
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Combination process-design strategies such as dummification and fill techniques at diffusion, poly, and in the back-end have been used historically to reduce systematic variation induced by the lithography, etch, and polish modules. The 45nm generation continued this improvement trend by extending the dummification and fill methodologies of past generations. Figure 14 illustrates this improvement by comparing poly dummification between 65nm and 45nm test vehicles.

Figure 14: Poly dummification improvements between 65nm and 45nm generations as demonstrated on a test vehicle
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Recent generations have seen the impact of non-uniformities at the poly layer extend beyond lithography, etch, and polish into modules such as RTA anneal [60]. Figure 15 shows an example of a combination design-process mitigation strategy where dummy features were incorporated to improve poly density and thus improve RTA temperature uniformity to reduce systematic transistor variation.

Figure 15: Dummy features were incorporated in 45nm generation to improve poly density and thus RTA temperature uniformity
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Design Mitigation Techniques

design mitigation techniques are techniques implemented by design and transparent to process. An example of a pure design mitigation technique used in the 45nm generation to reduce the impact of random variation is chopping, as shown in Figure 16. In chopping, the inputs to a differential amplifier are swapped, or chopped, under the control of a clock signal. The same clock signal is used to swap the outputs, and then the results are low-pass filtered.

Figure 16: Chopping was used in the 45nm generation as a pure design technique to mitigate the impact of random variation
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A more sophisticated design approach used in the 45nm generation to reduce the Vccmin impact of mismatch due to random variation in the SRAM was the incorporation of dynamic forward body bias (FBB) as shown in Figure 17. In this approach, the Nwell is partially discharged 1-cycle before the word-line by a programmable pulse. The Nwell then remains at lower bias during back-to-back access to minimize switching power. The SRAM PMOS FBB circuitry is integrated along the 8-column boundary and consumes less than 2% area overhead.

Figure 17: Use of SRAM PMOS FBB to reduce the Vccmin impact of mismatch due to random variation
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Systematic variation is best minimized through the use of good layout techniques. One of the design techniques used in the 45nm generation was to lay out matched devices so that they have the same centroid or center of gravity (see Figure 18); then, any device effect that manifests itself as a gradient across the layout will impact each set of matched devices equally.

Figure 18: Common centroid layouts were used in the 45nm generation as pure design techniques to mitigate the impact of systematic variation
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