Intel's 45nm CMOS Technology

  Section 2 of 9  

Managing Process Variation in Intel's 45nm CMOS Technology

INTRODUCTION AND HISTORICAL OVERVIEW

Moore's-Law-driven technology scaling has improved VLSI performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore's Law, a variety of challenges will need to be overcome. One of these challenges is management of process variation [1, 2].

Although there has been a trend in the CMOS literature in recent years to convey process variation as a new challenge associated with advanced CMOS technologies, that viewpoint does not effectively capture the history of process variation. Process variation has always been a critical aspect of semiconductor fabrication.

The first discussion of random variation in semiconductor devices was Shockley's 1961 analysis of random fluctuations in junction breakdown [3]. Shockley's concepts of random variation were extended to MOS devices by Keyes [4] in 1975 when he modeled the effect of random fluctuations in the number of impurity atoms in the depletion layer of a field-effect transistor (FET). Systematic variation in MOS devices was first addressed formally in 1974 by Schemmert and Zimmer [5] when they computed the sensitivity of ion-implanted MOS threshold voltages as a function of the implantation energy and the oxide thickness. A more extensive analysis of threshold voltage sensitivity using a closed-forum numerical simulation was presented by Yokoyama et al. in 1980 [6] with a Monte Carlo approach developed by Alvarez in the same year [7]. Interconnect variation has also received significant attention over the years, with Lin et al. presenting a detailed treatment in 1998 [8] that was expanded by many authors in the early 2000s [37, 40–43].

While the continued decrease in the ratio of feature sizes to fundamental dimensions (such as atomic dimensions and light wavelengths) means that management of variation will play a significant role in future technology scaling, the evidence shows that process variation has been a continuing theme throughout semiconductor history.

  Section 2 of 9  

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