Intel's 45nm CMOS Technology

Process and Electrical Results for the On-die Interconnect Stack for Intel's 45nm Process Generation

AUTHORS’ BIOGRAPHIES

Peter Moon
Peter Moon joined Intel in 1988 after completing his Ph.D. degree in Materials Science at MIT. He has worked on process integration for Intel's 0.8um, 0.35um, 130nm, and 45nm silicon process technologies including Intel's first use of shallow trench isolation (0.35um), copper interconnects (130nm), and Pb-free microprocessor products (45nm). Peter is currently leading the development of Intel's interconnect process for the 22nm process generation. His e-mail is peter.moon at intel.com.

Vinay Chikarmane
Vinay Chikarmane completed his B.Tech. degree in Chemical Engineering from IIT, Bombay and his Ph.D. degree in Materials Science from the University of Texas at Austin. He is currently a Principal Engineer in PTD, leads Copper Interconnect Development at the 32nm node, and is the Engineering Group Leader in the Thin Films area. He previously led Copper Interconnect Development at the 45nm, 65nm, and 90nm nodes, and he worked on engineering development of Intel's first Copper Technology (130nm) and the last two Aluminum Interconnect Technology nodes. His e-mail is vinay.b.chikarmane at intel.com.

Kevin Fischer
Kevin Fischer is a Senior Individual Contributor in PTD. He received his Ph.D. degree in Electrical Engineering from the University of Wisconsin at Madison. He has worked at Intel for seven years in process integration. Beginning on the 90nm process technology, he has worked on four different generations of back-end technology and is currently working on back-end process development for Intel's 22nm technology. His e-mail is kevin.j.fischer at intel.com.

Rohit Grover
Rohit Grover completed his B. Tech. degree in Engineering Physics from IIT Bombay in 1997, and he received M.S. and Ph.D. degrees in Electrical and Computer Engineering from the University of Maryland, College Park in 1999 and 2004, respectively. Since 2003, he has been working at Intel as a Senior Process Integration Engineer in the Far Back-end Group of Portland Technology Development. Rohit's team works on enabling lead-free, first-layer interconnects, managing packaging-induced low-k ILD stresses, and first-layer interconnect materials that are compatible with next-generation microprocessor architectures. His e-mail is rohit.grover at intel.com.

Tarek A. Ibrahim
Tarek A. Ibrahim joined Intel Corporation in 2004 after completing his Ph.D. degree in Electrical Engineering at the University of Maryland, College Park. He is a member of the Portland Technology Development integration group and worked on the interconnect process integration for the 45nm node. He is currently leading the focus team responsible for the interconnect patterning process of the 22nm process generation. His e-mail is tarek.a.ibrahim at intel.com.

Doug Ingerly
Doug Ingerly joined Intel in 2000. He holds a Ph.D. degree in Material Science and Engineering from the University of Wisconsin, Madison and a B.S. degree in Ceramic Engineering from the University of Missouri, Rolla. He has worked on process integration for Intel's 130nm and 65nm interconnect processes and led the far backend integration for the 45nm process. Currently, he is working on Intel's 22nm interconnect process. His e-mail is doug.b.ingerly at intel.com.

Kevin J. Lee
Kevin J. Lee is a Principal Engineer in Intel's Portland Technology Development Group, specializing in far back-end silicon processing. He was the technical lead for the thick MT9 redistribution layer process development. Prior to that he was Intel's Pb-free Bump Program Director, conducted Intel's initial copper damascene electroplating research and PbSn bump electroplating module development, and developed the buffer coat processes for Intel's 0.8um, 0.6um, and 0.35um technologies. He earned a B.A. degree from Hamline University in 1986 and a Ph.D. degree from the University of Illinois at Urbana-Champaign in 1991, both in Chemistry. His e-mail is kevin.j.lee at intel.com.

Chris Litteken
Chris Litteken joined Intel's Logic Technology Development organization in 2004 after completing his Ph.D. degree in Material Science from Stanford University. His research interests include the development of fracture mechanics methodologies to improve cracking/adhesion within thin-film structures. As a Senior Quality and Reliability Engineer, he develops predictive models for the thermo-mechanical reliability of 22nm, 45nm, and 65nm microprocessors and chipsets. His e-mail is christopher.s.litteken at intel.com.

Tony Mule
Tony Mule is a Senior Process Integration Engineer in the PTD BE Integration group. He received his M.S./Ph.D. degrees in Electrical Engineering from the Georgia Institute of Technology in 2004. Upon joining Intel, he has focused primarily on low-k dielectric patterning development for both the 45nm and 22nm technology generations. His e-mail is tony.v.mule at intel.com.

Sarah Williams
Sarah Williams is an etch group leader in Intel's Logic Technology Development organization. She joined Intel in 2000 after completing her Ph.D. in Physical Chemistry at the University of Wisconsin-Madison. She is currently working on the development of interconnect processes for the 32nm logic technology. Her e-mail is Sarah.A.Williams at intel.com.

Back to Top