Intel's 45nm CMOS Technology

Process and Electrical Results for the On-die Interconnect Stack for Intel's 45nm Process Generation

REFERENCES

[1] K. Mistry et al., "A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning and 100% Pb-free Packaging." IEDM Technology Digest, 2007, pps. 247–250.

[2] P. Bai et al., "A 65nm Logic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-K ILD, and .57um SRAM Cell." IEDM Technology Digest, 2004, pps. 657–666.

[3] A. Yeoh et al., "Copper Die Bumps (first level Interconnect) and Low-K Dielectric in 65nm High Volume Manufacturing." In ECTC Proceedings, 2006.

[4] M. Renavikar et al., "Materials Technology for Environmentally Green Micro-electronic Packaging." Intel Technology Journal, Volume 12, Issue 1, 2008.

[5] "Temperature Cycling." JESD22-A104-C, May 2005.

[6] "Accelerated Moisture Resistance—unbiased HAST." JESD22-A118, December 2000.

[7] "Highly Accelerated Temperature and Humidity Stress (HAST)." JESD22-A110-B, February 1999.

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