Intel's 45nm CMOS Technology

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Process and Electrical Results for the On-die Interconnect Stack for Intel's 45nm Process Generation

DISCUSSION

Interconnect design is a compromise between density, RC performance, and cost: narrow wires deliver high-density but relatively poor RC performance, while wide wires have better RC performance but reduced density. Extra metal layers can improve either density or RC performance, but they also add process cost. High-performance logic products are designed with fine pitch wires at the lower layers where density is critical, and with wide/thick wires at the upper layers where RC performance is critical.

Intel's 45nm interconnect process uses a unique solution to the problem of interaction between density, RC performance, and cost, by adding a low-cost, very-low-resistance layer to improve the power distribution network at the upper metal layers. The reduced requirement for power distribution in the MT6, MT7, and MT8 layers and the move to low-k dielectric at MT6 and MT7 enables these layers to allocate more chip area to signal wires, resulting in improved RC performance, without adding process cost.

The lower metal layers use 160nm pitch with dry 193nm lithography to achieve high density with acceptable RC performance and relatively low process cost. The tungsten-filled local interconnect layer beneath MT1 helps to achieve high density. The re-use of robust dielectric materials with optimized thickness improves RC performance at the lower metal layers while maintaining high reliability and controlling process cost.

The new process exceeds the reliability requirements for high-volume manufacturing. The 45nm process with its seven layers of low-k dielectrics has significant intrinsic margins to film cracking and/or interface delamination even with the increased stress of a Pb-free process. The MT9 redistribution layer has excellent EM performance on its own and enables redundancy between Cu bumps, which effectively improves their EM resistance as well. The complete interconnect stack is capable of withstanding temperature shock, HAST, and PreCon stresses, all of which exceed end-of-life goals [5, 6, 7].

  Section 4 of 8  

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