Intel's 45nm CMOS Technology

Process and Electrical Results for the On-die Interconnect Stack for Intel's 45nm Process Generation

RESULTS

The 45nm process delivers reduced capacitance relative to the previous 65nm process generation through a combination of techniques. The newer process replaces SiO₂ dielectric with low-k CDO dielectrics at MT1, MT6, and MT7 for a >20% capacitance improvement at those layers as shown in Figure 4. Also, at the lower metal layers, the SiCN etch stop layer is aggressively scaled for an additional 5% capacitance reduction. Overall, the newer process achieves a 10% average capacitance improvement while re-using the robust CDO dielectric film and capital equipment from the previous process generation.

Figure 4: Capacitance comparison between the 45nm process and 65nm process
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It is important to accurately benchmark interconnect RC performance. Interconnect capacitance and resistance are measured for minimum pitch lines with 50% dense, minimum-pitch metal patterns directly above and below the measured feature. Total capacitance is the sum of line-line capacitance and layer-layer capacitance as indicated in Figure 5.

Figure 5: Components of capacitance measurement
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Measured capacitance and resistance values for the 45nm process are shown in Figures 6 and 7 at the MT2 and MT6 layers, respectively. The MT2 layer delivers median values of 0.20 fF/um total capacitance and 3.3 ohm/um resistance at 160nm pitch. Resistance at lower metal layers includes a 10% resistance penalty to enable high current density without electromigration failures for high-performance logic products. The MT6 process delivers median values of 0.21 fF/um total capacitance and 0.38 ohm/um resistance at 360nm pitch.

Figure 6: R and C values for MT2 at 160nm pitch
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Figure 7: R and C values for MT6 at 360nm pitch
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The thick MT9 lines allow for neighboring bumps to be connected by a low-resistance path that enables current redistribution upon initial electromigration (EM) damage at individual bump/solder joints. The large cross-section area of MT9 and its excellent electromigration resistance achieves redundancy of neighboring bumps without concern for electromigration in MT9 itself. Figure 8 shows an electromigration Time-to-Failure comparison between a single daisy chain of C4 bumps vs. two daisy chains of bumps tested in parallel, connected through MT9 with twice the amount of current; and both tested under accelerated conditions of higher temperature and higher current. As the plot indicates, MT9 redundant layout increases bump EM performance by at least 1.65X. Due to long testing periods, the stress ended without any redundant links failing. These data show that MT9 delivered the desired bump EM improvement. 

Figure 8: EM fail rate for redundant Cu bumps
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Figure 9 shows a Confocal Scanning Acoustic Microscope (CSAM) image of a product unit (full stack) taken after packaging with Sn-Ag-Cu solder. Areas of cracking or interface delamination will show up as white or black spots apart form the contrast variation of the underlying pattern. As seen in Figure 9, no contrast areas are observed, which shows that the unit is free of cracking or interface delamination. These results have been demonstrated on thousands of units and across the expected process variations.

Figure 9: CSAM image of a production unit post packaging
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It is critical that this thick MT9 layer also be reliable in addition to achieving electrical benefits. Figure 10 shows a CSAM of the MT9/VA9 layer after 25 hours of HAST stress; the image is clean of any delamination or cracking.

Figure 10: CSAM image of a production unit after 25 hours of HAST
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