Intel's 45nm CMOS Technology

Process and Electrical Results for the On-die Interconnect Stack for Intel's 45nm Process Generation

INTRODUCTION

The density and performance of the on-die interconnect stack must continue to improve with each process generation to support increasingly powerful and compact microprocessors. At the same time, process costs must be strictly controlled. The on-die interconnect stack for Intel's 45nm process generation extends the dual damascene processing scheme used on previous generations and adds several innovations for increased density and performance [1].

A new, low-cost and low-resistance Metal-9 layer (MT9) is formed on top of the conventional interconnect stack to support improved power distribution between the C4 bumps and the other metal layers. This MT9 redistribution layer is formed by copper plate-up between sacrificial photoresist lines in a similar fashion to C4 bump formation. The MT9 layer is covered by a silicon nitride passivation layer, a polymer dielectric, and finally, the copper C4 bumps.

The Metal-1 to Metal-3 (MT1–MT3) layers use 193nm dry lithography with 160nm pitch to achieve high-density wiring with lower process cost than immersion lithography. These metal layers also achieve low capacitance due to aggressive scaling of the SiCN etchstop film along with use of carbon doped oxide (CDO) low-k dielectric. The median RC performance for the MT2 layer is 0.20fF/um capacitance and 3.3ohm/um resistance at 160um pitch, as measured on the high-volume manufacturing process with electromigration performance that is consistent with the requirements of high-performance microprocessors.

Overall, the on-die interconnect stack for the 45nm process generation delivers 2X higher area density, 10% lower average capacitance, improved power distribution, and a completely Pb-free product.

Process Discussion

The on-die MT1–MT7 interconnects are formed by dual damascene patterning with highly manufacturable low-k CDO dielectrics. The lower layer metal pitches are 160nm, while upper layer metal pitches increase progressively to optimize density and performance as shown in Table 1 and Figure 1. MT8 is also formed by dual damascene patterning, but it uses PECVD SiO₂ as the dielectric film, and the MT8 layer is covered with a thick PECVD silicon nitride film.

Table 1: Layer material, pitch, thickness and aspect ratio
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Figure 1: SEM image of interconnect stack up to MT8
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The MT9 redistribution layer is formed using a plate-up process. It begins by depositing a blanket Barrier/Seed (Ti/Cu) layer over the entire wafer. The MT9 line/space pattern is created using a thick photoresist followed by standard Cu electroplating to form the MT9 lines. The resist is then stripped and the Barrier/Seed between MT9 lines is removed. The finished MT9 wires are capped with a 400nm PECVD silicon nitride film for improved isolation.

The MT9 layer is covered with 16um of a spin-on polymer dielectric that is patterned by standard lithography techniques and cured in a furnace. From this point onwards the processing is very similar to that used to form the Cu bumps utilized in the 65nm process [2, 3]. Figure 2 shows a cross-section view of the MT9, VA9, and Cu bump layers.

Figure 2: SEM image detailing the MT9 and VA9 layers
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After Cu bump formation, the wafers are tested, diced into individual die, and assembled into packaged units. The electrical connection between die and package uses a Pb-free solder as shown in Figure 3. Details of this process are described elsewhere [4].

Figure 3: SEM image showing a Bump post chip attach
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