Intel's 45nm CMOS Technology

Process and Electrical Results for the On-die Interconnect Stack for Intel's 45nm Process Generation

Peter Moon, Technology Manufacturing Group, Intel Corporation
Vinay Chikarmane, Technology Manufacturing Group, Intel Corporation
Kevin Fischer, Technology Manufacturing Group, Intel Corporation
Rohit Grover, Technology Manufacturing Group, Intel Corporation
Tarek A. Ibrahim, Technology Manufacturing Group, Intel Corporation
Doug Ingerly, Technology Manufacturing Group, Intel Corporation
Kevin J. Lee, Technology Manufacturing Group, Intel Corporation
Chris Litteken, Technology Manufacturing Group, Intel Corporation
Tony Mule, Technology Manufacturing Group, Intel Corporation
Sarah Williams, Technology Manufacturing Group, Intel Corporation

Index words: 45nm, process technology, copper

Citations for this paper: Chikarmane, V.; Fischer, K.; Grover, R.; Ibrahim, T.; Ingerly, D.; Lee, K.; Litteken, C.; Moon, P.; Mule, T.; Williams, S. "Process and Electrical Results for the On-die Interconnect Stack for Intel's 45nm Process Generation." Intel Technology Journal. http://www.intel.com/technology/itj/2008/
v12i2/2-process/1-abstract.htm (June 2008).

ABSTRACT

This paper introduces the issues associated with on-die interconnects and describes how they are addressed on Intel's 45nm high-performance, logic process technology. The 45nm process generation uses carbon-doped oxide low-k dielectric and aggressive scaling of the silicon-carbide-nitride (SiCN) etchstop film to achieve a 10% average capacitance reduction at the MT1-MT8 layers, relative to the previous 65nm generation. A thick MT9 layer is added to provide a low resistance path for power routing. MT1-MT8 interconnect RC performance benchmarking and the process and reliability concerns associated with the MT9 redistribution layer are discussed. The combined MT1-MT9 interconnect stack provides high performance and high reliability and enables a completely lead-free (Pb-free) product.

Back to Top