Intel's 45nm CMOS Technology

  Section 8 of 11  

45nm High-k+Metal Gate Strain-Enhanced Transistors

CONCLUSION

High-k+metal gate transistors have been integrated into a manufacturable 45nm process for the first time. Selection of the metal-gate flow (high-k first, metal-gate last) was made to maximize the benefit from the strained silicon steps. Novel stress techniques were also developed to replace the stress methods that are compromised due to scaling and the metal gate flow. The scaling of the transistor density was achieved through development of new poly and contact patterning schemes The resultant transistors provide record drive current at low leakage and at tight contacted gate pitch achieving both performance and density benefits. This is demonstrated in the ring oscillators with a 23% gate delay reduction compared to 65nm at the same Ioff and 10% lower VDD.

  Section 8 of 11  

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