Intel's 45nm CMOS Technology

45nm High-k+Metal Gate Strain-Enhanced Transistors

RING OSCILLATORS

The transistor performance gains are reflected in the ring oscillator performance data. Gate delay data from ring oscillators with a fanout of 2 is benchmarked at 100nA/µm Ioff each for NMOS and PMOS, at 1.2V for 65nm and a lower 1.1V for 45nm. The ring oscillators use the minimum contacted gate pitch (220nm and 160nm) for each technology. Despite the scaling of both voltage and gate pitch, FO=2 gate delay is reduced from 6.65pS (65nm) to 5.1pS (45nm), for a gain of 23% (Figure 20). Table 3 breaks out the RO gains between NMOS/PMOS Idsat, Idlin, and the gate and junction capacitances, illustrating the marked impact of the PMOS performance gains on the ring oscillators.

Figure 20: Ring oscillator delay vs. leakage for fanout=2. Comparison of delay for 65nm vs. 45nm is at 1.2 and 1.1V, respectively.
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Table 3: Breakdown of RO gains vs. 65nm results. The voltage scaling term accounts for the reduction in VDD from 1.2V (65nm) to 1.1V (45nm).
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