Intel's 45nm CMOS Technology

45nm High-k+Metal Gate Strain-Enhanced Transistors

STRESS ENHANCEMENT IN A METAL GATE FLOW

Since its introduction at the 90nm node, strain has become a central performance enhancement element for the standard CMOS flow. The most commonly used techniques for implementing strain in the transistors include embedded SiGe in the PMOS S/D, stress memorization for the NMOS, and a nitride stress-capping layer for NMOS and PMOS devices (Table 2).

Table 2: Comparison of stress enhancement methods for 65nm and 45nm nodes. New features are highlighted in bold.
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A key benefit of using a gate-last flow comes from removing the poly gate from the transistor after the stress-enhancement techniques are in place. It has been shown that the stress benefit from the embedded S/D SiGe process is enhanced through this removal of the poly gate, since the poly gate acts as a buffer counteracting the effect of the embedded S/D SiGe [9]. This benefit can be illustrated in simulation with an estimated 50% increase in lateral compressive stress by removal of the polysilicon gate (Figure 17). The combined impact of the increased Ge fraction in the embedded S/D and the strain enhancement from the gate-last process allow for a 1.5x higher hole mobility compared to 65nm, despite the scaling of the transistor pitch from 220nm to 160nm.

Figure 17: Stress contours in the PMOS transistor before and after the removal of the polysilicon dummy gate. Stress in the channel is shown to increase 50% from 0.8GPa to >1.2 GPa.
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For the NMOS device, two methods of stress enhancement have been employed in this technology. First, the loss of the nitride stress layer benefit, due to scaling the pitch from the 65nm technology node, has been overcome by the introduction of trench contacts and by tailoring the contact fill material to induce a tensile stress in the channel. The NMOS response to tensile (control) vs. compressive contact fill materials is shown in Figure 18. The stress impact of the trench contact fill material on the PMOS device is mitigated by use of the raised S/D inherent in the embedded SiGe S/D process.

Figure 18: Ion-Ioff benefit of tensile contact fill showing a 10% NMOS Idsat benefit. Contact resistance is matched for the two fill materials.
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For NMOS stress memorization, there are two primary methods commonly used, one is memorization of stress in the (S/D) of the device and the other is memorization in the poly gate [10]. The metal gate-last flow is compatible with the S/D method while the poly gate component would be compromised. To compensate for this, the poly gate component is replaced by Metal Gate Stress (MGS). i.e., modifying the metal-gate fill material to directly induce stress in the channel [11]. By introducing a gate fill material with a compressive stress, the performance of the NMOS device is enhanced and adds to the contact fill technique (Figure 19). By use of a dual-metal process with PMOS first, the stress of the NMOS gate is decoupled from the PMOS gate through optimization of the PMOS gate stack to buffer the stress.

Figure 19: Ion-Ioff benefit of compressive gate stress showing a 6% NMOS Idsat gain. Tensile contact fill is used on both sets of data.
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