Intel's 45nm CMOS Technology

45nm High-k+Metal Gate Strain-Enhanced Transistors

TRANSISTOR RESULTS

The introduction of the high-k gate dielectric delivered a dramatic gate leakage reduction relative to 65nm transistors of >25X for NMOS and 1000X for PMOS (Figure 8).

Figure 8: Gate leakage reduction of 25-1000x with use of high-k+metal gate relative to 65nm technology
 

The high-k+metal gate transistors exhibit excellent short channel characteristics due to the combination of Tox scaling and the optimal workfunction metal gates (Figures 9 and 10). The excellent gate control is also illustrated in the well-behaved subthreshold characteristics (Figure 11).

Figure 9: NMOS Vt vs. Lg shows excellent SCE and DIBL
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Figure 10: PMOS Vt vs. Lg shows excellent SCE and DIBL
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Figure 11: Subthreshold Id-Vgs for both NMOS and PMOS transistors
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PMOS performance is improved by using high-k+metal gate as well as by the enhancements to the embedded SiGe processing. The PMOS drive current (Figure 12) of 1.07 mA/µm is a marked 51% improvement over 65nm [8]. NMOS drive current (Figure 13) is 1.36mA/µm, 12% better than the previous-generation, 65nm transistors. The average drive current improvement versus 65nm is 32% at the same voltage and Ioff, despite scaled transistor pitch. The linear drive currents show similar enhancements with PMOS (Figure 14) at 0.178mA/µm and NMOS (Figure 15) at 0.192mA/µm. These drive currents are benchmarked at 1.0V, a low 100nA/µm Ioff and at 160nm contacted gate pitch. Both the saturated and the linear drive currents represent the best drive currents reported to date for a 45nm technology at low Ioff. Figure 16 shows the transistor performance vs. gate pitch for this generation illustrating that both density and performance are improved with this transistor flow.

Figure 12: PMOS Idsat of 1.07mA/µm at 100nA/µm Ioff and Vdd =1.0V
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Figure 13: NMOS Idsat of 1.36mA/µm at 100nA/µm Ioff and Vdd =1.0V
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Figure 14: PMOS Idlin of 0.178mA/µm at 100nA/µm Ioff and Vds=0.05V
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Figure 15: NMOS Idlin of 0.192mA/µm at 100nA/µm Ioff and Vds=0.05V
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Figure 16: Performance vs. gate pitch for 90, 65, and 45nm generations
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