Intel's 45nm CMOS Technology

  Section 4 of 11  

45nm High-k+Metal Gate Strain-Enhanced Transistors

DESIGN RULES AND 193NM DRY PATTERNING

Contacted gate pitch is a key measure of front-end density, and the scaling to 160nm maintains the 0.7x scaling trend (Figure 5). This is the most aggressive contacted gate pitch reported to date for a 45nm high-performance logic technology. The contact process has also been modified, with trench contacts replacing conventional contacts for lower series resistance. Trench-contact-based local routing improves layout density, especially for cross-coupled inverter pairs that are very common in microprocessor SRAM and register file arrays. Tight pitches and trench contacts allow SRAM cell size to be scaled to 0.346µm² (Figure 6).

Figure 5: Contacted gate pitch and SRAM cell size scaling trend for Intel's technology nodes
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Figure 6: Diffusion and poly layers for 0.346 µm2 6-T SRAM cell
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In order to enable these tight pitches by use of low-cost 0.92NA 193nm dry patterning, innovative processes were developed to produce robust patterning. This is demonstrated by the fidelity of the poly lines in Figure 6. The gate patterning process uses a double patterning scheme. Initially the gate stack is deposited including the polysilicon and hardmask deposition. The first lithography step patterns a series of parallel, continuous lines. Only discrete pitches are allowed, with the smallest at 160nm, to assist in the patterning. A second masking step is then used to define the cuts in the lines. The two-step process enables abrupt poly endcap regions, devoid of rounding that allows for tight contact-to-gate design rules (Figure 7). There are no additional masking steps from this process, since the 65nm generation also used two reticles for poly patterning.

Figure 7: Top-down SEM post-poly-patterning process showing 160nm poly pitch with minimum gate length lines. Note the square poly ends, devoid of rounding.
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The contact patterning process uses a similar pitch restriction to facilitate lithography. Trench diffusion contacts run parallel to the gates with discrete pitches, while trench gate contacts run orthogonal to the gates. Use of trench contacts has the added benefits of lowering the contact resistance by >50% and allowing their use as a local interconnect, which improves SRAM/logic density by up to 10%.

  Section 4 of 11  

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