Intel's 45nm CMOS Technology

45nm High-k+Metal Gate Strain-Enhanced Transistors

TRANSISTOR PROCESS FLOW

The two common methods for introducing a metal gate to the standard CMOS flow include either a "gate-first" or "gate-last" process. Most comparisons of these two process flows focus on the ability to select the appropriate workfunction metals, the ease of integration, or the ability to scale; however, these comparisons typically fail to comprehend the interaction of the process flows with the strain-inducing techniques. By use of a high-k first and metal gate-last flow, it is possible to maximize the benefits of the stress-inducing steps and high temperature junction formation, while minimizing the thermal processing of the workfunction metals.

In the metal gate-first flow (Table 1), the high-k dielectric and dual-metal processing are completed prior to the polysilicon gate deposition. The dual metal gates are then subtractively etched along with the poly gates prior to Source/Drain (S/D) formation. In contrast, for the high-k first and metal gate-last flow used in this work, a standard polysilicon gate is deposited after the hafnium-based, high-k gate dielectric deposition (Figure 2). This is followed by a standard polysilicon processing flow through the salicide formation steps.

Table 1: Comparison of unique steps in gate-first and high-k first, metal gate-last process flows. Key differences are highlighted in bold.
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Figure 2: TEM of high-k/metal gate stack
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After deposition of the contact etch stop and the first Interlayer Dielectric (ILD) films, a polish step is used to expose the poly gates and enable removal of the dummy poly. The PMOS workfunction metal is then deposited. A patterning step removes the PMOS metal from the NMOS area. The NMOS workfunction metal is deposited, and the gate trenches are filled with Al for low gate resistance. By using novel gap-fill techniques, robust gate resistance is enabled to sub-30nm gate lengths (Figure 3). A metal polish step is used to remove the excess metal and planarize the gate trenches. The flow then continues with the contact and interconnect processing steps.

Figure 3: Gate sheet rho versus gate length showing scalability of gate fill process
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Figure 4 shows a TEM of the high-k/metal gate NMOS and PMOS transistors with the embedded SiGe S/D strain layer on the PMOS and Ni salicide. The strained silicon techniques that Intel first introduced at the 90nm and 65nm nodes were further enhanced in this generation. The Ge concentration of the embedded SiGe S/D was increased to 30% from the previous generations of 23% in Intel's 65nm technology [6] and 17% in the 90nm technology [7].

Figure 4: TEMs of high-k+metal gate NMOS and PMOS transistors
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