Intel's 45nm CMOS Technology

45nm High-k+Metal Gate Strain-Enhanced Transistors

INTRODUCTION

One of the key methods to enable transistor gate length scaling over the past several generations has been to scale the gate oxide. This improves the control of the gate electrode over the channel, enabling both shorter channel lengths and higher performance. As the gate oxide was scaled the gate leakage increased; this increase in gate leakage was insignificant until the 90nm technology node (Figure 1). At the 90nm and 65nm nodes, the scaling of the gate oxide slowed as a result of the power limitations from the increase in gate leakage. In order to overcome this at the 45nm technology, a gate dielectric with a higher dielectric constant (high-k) has been introduced. This enabled a >25x gate leakage reduction while scaling the Tox by 0.7x.

Figure 1: Trend of inversion Tox and gate leakage vs. Intel technology node
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The introduction of high-k gate dielectrics has been slowed by several issues [2–4]. The first was the interaction by the high-k material with the existing polysilicon gates. This interaction led to high trap densities at the interface that pinned the Vt of the transistor to an undesirable value. The second was the degradation of the channel mobility in the presence of high-k dielectrics. The third issue was the poor reliability of the high-k dielectric.

The gate electrode effectiveness has also been increasingly impacted by poly depletion effects. This has led to lower drive currents when the transistor is turned on. By selecting a compatible metal gate electrode with the high-k gate dielectric, both the poly depletion effects and the Vt pinning at the high-k/polysilicon interface can be eliminated while providing higher channel mobilities [5].

In introducing high-k+metal gate transistors for the 45nm generation, these significant challenges needed to be overcome. First, we had to determine which material to use for the high-k dielectric and find dual-band edge metals that were compatible with that high-k dielectric. Second, an integrated CMOS flow needed to be developed that matched the channel mobility of SiO₂ while meeting the reliability requirements for the technology. The development of this CMOS flow was complicated by the need to mesh the process requirements of the metal gate process with both the thermal limitations of the junction formation steps and the uniaxial strain-inducing steps, both of which have become central to the transistor architecture.

Along with the above-mentioned improvements in performance and gate leakage with high-k+metal gate, a key requirement of the technology node was an increased packing density for the transistors. For each node, an ~50% area scaling is expected, and this technology continues that trend. A key challenge to overcome in this scaling is the loss of performance due to scaling of the stress-inducing features of the technology. Use of 193nm dry lithography for critical layers at the 45nm technology node was preferred over moving to 193nm immersion lithography, due to lower cost and greater maturity of the toolset. In order to achieve the tight 160nm gate and contact pitch requirements, unique gate and contact patterning process flows were developed and implemented.

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