Intel's 45nm CMOS Technology

45nm High-k+Metal Gate Strain-Enhanced Transistors

AUTHORS’ BIOGRAPHIES

Chris Auth
Chris Auth joined Intel in 1997 after completing his Ph.D. degree in Electrical Engineering from Stanford University. He initially developed the NOR flash cell for Intel's 0.18µm node. After joining Portland Technology Development in 2000, he developed the industry's first use of strain for transistor enhancement at the 90nm and 65nm nodes. At the 45nm node, he led the process development and introduction of the industry-first, high-k/metal-gate process. He has received two IAAs, holds five US Patents, and has authored/co-authored 18 publications. His e-mail is chris.auth at intel.com.

Mark Buehler
Mark Buehler received his B.S. degree in Chemical Engineering from the University of California at Berkeley. He then completed his M.S. and Ph.D. in Chemical Engineering at the University of Washington. In 1995, he joined the Portland Technology Department of Intel Corporation. He has worked in both metal and oxide CMP process development since Intel's 0.25µm technology node. He is currently working on metal CMP for Intel's 32nm and 22nm nodes. His e-mail is mark.buehler at intel.com.

Annalisa Cappellani
Annalisa Cappellani is a Senior Integration Engineer in the Portland Technology Development Department. She joined Intel in 2001 after receiving a Ph.D. degree from the University of Newcastle (UK). She conducted all her Ph.D. work on Poly/metal gate for advanced RF CMOS and DRAM in Germany at Siemens AG research labs (Munich) and at Infineon AG development fab (Dresden). As a member of PTD group at Intel she has been responsible first for the introduction of NiSi in the 90nm and then of the Metal Gate integration in 45nm logic technology. Annalisa is currently working on the pathfinding for the 22nm logic technology node. Her e-mail is annalisa.cappellani at intel.com.

Chi-hing Choi
Chi-hing Choi joined Intel in 1991 after completing a Ph.D. degree in Materials Science and Engineering at Northwestern University. He has worked on developing metal gate deposition technologies since 2003. His e-mail is Chi-hing.Choi at intel.com.

Gary Ding
Gary Ding joined Intel in 1994 after completing his Ph.D. degree in Materials Science and Engineering at Cornell University. He has worked on metal interconnect, salicide, electroplating, and planarization projects. He is currently a planarization group leader in Portland Technology Development responsible for front end planarization. His e-mail is gary.ding at intel.com.

Weimin Han
Weimin Han joined Intel in 1991 after completing a Ph.D. degree in Physics at Oregon State University. He is a Diffusion Group Leader in Intel's Logic Technology Development organization and worked on diffusion process development since Intel's 0.8µm process technology. He is currently responsible for developing an advanced ALD/CVD batch deposition process for the 32/25nm CMOS node. His e-mail is Weimin.c.Han at intel.com.

Subhash M. Joshi
Subhash M. Joshi joined Intel in 2000 after completing a Ph.D. degree in Materials Science at Duke University. He worked on integrating low-k dielectrics with flip-chip packaging and improving C4 bump reliability on Intel's 90nm technology, together with early development of the lead-free bump and redistribution layer modules. Since 2004, he has worked on front-end process integration, including development of shallow trench isolation, dual metal gate, and trench contact modules for Intel's 45nm technology. His e-mail is subhash.m.joshi at intel.com.

Brian McIntyre
Brian McIntyre is an Etch Group Leader in Intel's Logic Technology Development organization. He joined Intel in 1994 and has worked on etch process development since Intel's 0.35µm process technology. He is currently responsible for developing patterning processes for the 22nm CMOS node. He received his Ph.D. degree from the University of California, Berkeley in 1994. His e-mail is brian.mcintyre at intel.com.

Matt Prince
Matt Prince joined Intel in 1988 after graduating from Clarkson University. He has developed CMP processes, consumables, and equipment for Intel's 0.8µm to 45nm technology nodes. He has developed STI, ILD, W, Cu, and poly CMP processes for Intel's logic technologies.

Pushkar Ranade
Pushkar Ranade joined Intel in 2003 after graduating with a Ph.D. degree from the University of California, Berkeley. At Berkeley, his research was in the area of sub-70nm CMOS transistor design and involved the integration of novel gate stack materials and ultra-shallow junctions. Since joining Intel, he has worked on transistor integration and development of Intel's 65nm and 45nm technology nodes, and he is currently working on the 22nm technology node. He has authored or co-authored over 35 technical publications and holds 4 U.S. patents. His e-mail is pushkar.ranade at intel.com.

Justin Sandford
Justin Sandford joined Intel in 1994 after graduating from Arizona State University. He has worked on the front-end process integration of Intel's silicon process technology beginning at the 0.25µm node. Justin is currently working on the development of Intel's 22nm Logic Technology. His e-mail address is Justin.S.Sandford at intel.com.

Christopher Thomas
Christopher Thomas joined Intel in 1997 after completing his Ph.D. degree in Physics from Northwestern University. He supported thin film technology development for the 0.18µm, 90nm, and 45nm nodes. He holds nine US patents. He is currently the High-k Deposition Group Leader, and for the past five years has been responsible for developing the gate oxide deposition process. His e-mail is christopher.d.thomas at intel.com.

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