Intel's 45nm CMOS Technology

45nm High-k+Metal Gate Strain-Enhanced Transistors

REFERENCES

[1] K. Mistry, et al., "A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging." IEDM Technical Digest, 2007, pp. 247–250.

[2] V. Misra, G. Lucovsky, & G. Parsons, "Issues in High-k Gate Stack Interfaces." MRS Bull., Vol. 27, No. 3, 2001, pp. 212–216.

[3] C. Hobbs et al., "Fermi Level Pinning at the Poly-Si/Metal Oxide Interface." Symposium on VLSI Technology Digest, 2003, pp. 9–10.

[4] G. Ribes et al., "Review on High-k Dielectrics Reliability." IEEE Transactions on Device and Materials Reliability, Vol. 5, No. 1, 2005, pp. 5–19.

[5] R. Kotlyar et al., "Inversion Mobility and Gate Leakage in High-k/Metal Gate MOSFETs." IEDM Technical Digest, 2004, page 391.

[6] P. Bai et al., "A 65nm Logic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-k ILD and 0.57 um2 SRAM Cell." IEDM Technical Digest, 2004, pp. 657–660.

[7] T. Ghani et al., "A 90nm high-volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors." IEDM Technical Digest, 2003, pp. 978–980.

[8] S. Tyagi, et al., "An advanced low power, high performance, strained channel 65nm technology." IEDM Technical Digest, 2005, pp. 1070–1072.

[9] J. Wang, et al., "Novel Channel-Stress Enhancement Technology with eSiGe S/D and Recessed Channel on Damascene Gate Process." Symposium on VLSI Technology Digest, 2007, pp. 46–47.

[10] A. Wei, et al., "Multiple Stress Memorization in Advanced SOI CMOS Technologies." Symposium on VLSI Technology Digest, 2007, pp. 216–217.

[11] C. Kang, et al., "A Novel Electrode-Induced Strain Engineering for High Performance SOI FinFET utilizing Si (110) Channel for Both N and PMOSFETs." IEDM Technical Digest, 2006, pp. 885–888.

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