Technology with the Environment in Mind

Materials Technology for Environmentally Green Micro-electronic Packaging

PB-FREE INITIATIVE: SECOND LEVEL INTERCONNECT MATERIALS (2LI)

Another critical challenge to meet EU RoHS requirements in Intel's packaging technology was the transition to Pb-free solder technology for 2LI applications. 2LI refers to the interconnect between the substrate and the printed wiring board (PWB). 2LI is accomplished with solder sphere, flux and/or paste, and it involves two reflow processes: ball attachment (BA) and surface-mount reflows for board attach. In the BA process, paste is printed onto the metal pad on the BGA side of the substrate, typically by using screen printing. Then solder spheres are picked and placed onto the paste printed pads. Finally, substrates with solder balls undergo a reflow process, typically in a multizone convective oven. In the surface process, solder paste is applied onto the metal pad on the PWB, typically by using stencil printing. Solder ball-attached packages are then picked and placed onto the fluxed PWB. Finally, the entire package and PWB undergo a reflow process typically in a multizone convective oven. Traditionally, eutectic tin-lead alloy was used for 2LI solder metallurgy applications. Relatively low melting temperatures (T_m = 183°C) and excellent shock resistance of the eutectic Sn-Pb alloy made this alloy highly suitable for Pb-ed BGA applications. Several Pb-free solder alloys for BGA applications were evaluated for this purpose, and SAC405 (tin-4% Ag- 0.5% Cu) was downselected based upon extensive materials characterization and reliability evaluations. The SAC405 solder alloy has a higher melting temperature (217-221°C) than eutectic SnPb solders, as well as a higher elastic stiffness and yield strength. These differences in the physical and mechanical properties of SAC405 solder alloy posed several challenges to packaging processes and reliability performance, especially due to the need to reflow the solder alloys at much higher temperatures (230-260°C peak reflow temperatures) than those used for eutectic SnPb. Figure 2 shows a typical SAC solder alloy reflow profile (BA and SMT) used for SnAgCu solder.

Figure 2: Typical SAC solder alloy reflow profile (BA and BGA)
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The transition to Pb-free solders also necessitated a change in the composition of the paste from eutectic SnPb to SAC405 metal powder paste for BA and surface-mount applications. This change in paste composition forced the need to optimize the fluxability of the flux in the paste to ensure robust solder joint formation in conjunction with the SAC405 solder BGA spheres. Higher processing temperatures necessitated the use of appropriate solder paste/flux formulations that could withstand the higher thermal exposure and facilitate excellent joint formation with a myriad of surface finishes such as Electroless Nickel Immersion Gold (ENIG), Cu OSP (Organic Surface Protection), and Immersion Silver (ImAg). The use of SAC solder alloy for BGA applications has the potential to impact both the package- and board-level manufacturing and reliability. Additionally, Intel's packages also utilize paste for attaching BGA spheres to the packages. As mentioned earlier, the need to reflow SAC solders at higher temperatures impacts the package and board materials manufacturing to enable high temperature reflow. In addition to the metallurgical challenges involved in the high temperature reflow of 2LI solder joints, the impact of high temperature reflow on the viscoelastic behavior of the package and board-level materials and accompanying reliability concerns needed to be understood. In the next section, we discuss the 2LI solder joint reliability challenges and board-level surface-mount challenges due to the transition to Pb-free materials.

Pb-free Initiative: 2LI Reliability Challenges

A failure-mechanism-based approach was used for Lead-free (LF) 2LI reliability assessment. An LF material property comparison was made with SnPb solder to understand the failure-mechanism-based reliability risks. The typical LF reliability concerns based on the failure mechanism and stress testing approach are listed in Table 1.

Table 1: LF failure concerns and recommended stress testing
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LF 2LI reliability challenges include delamination with increased reflow temperature (35° C higher than Sn/Pb), lower mechanical margin in high strain rate shock testing due to increased stiffness (1.5 times stiffer than SnPb solder), creep performance difference compared to SnPb, and Sn whiskers. The JEDEC specification for max reflow spec of 260° C was established as part of the solution, and Intel components were qualified to meet the JEDEC specification for peak reflow requirements. Use-condition-based reliability performance was used for Pb-free alloy selection. The LF mechanical margin was lower than that for SnPb solder, but it passed intensive board-level shock and vibe testing. The mechanical margin testing showed lower mechanical performance compared to SnPb solder, and the results are shown in Figure 3. The NCTF design rule was implemented at corner joints for shock margins.

Figure 3: Mechanical margin assessment for LF solder
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The failure mode during shock is manifested in cracking along the solder joint (either on the package or board side) as shown in Figure 4 [1].

Figure 4: SAC405 solder joint failure in shock conditions
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A detailed failure analysis reveals that the shock crack in SAC is along the interface between the IMC and the solder (package side) and through the IMC bulk (board side). In either case, shock failure is characterized by a lack of solder deformation and an absence of solder bulk cracking. This is quite contrary to thermal fatigue failure where the solder joint exhibits extensive inelastic deformation that is often time-dependent.

This difference is partly due to the strain-rate sensitivity of metallic materials. Metallic materials including solders typically become stronger with increasing strain rates. In other words, the flow stress increases with increasing strain rates. The strain rate sensitivity is a strong function of the homologous temperature(Thom), which is considerably higher for solders, due to their low melting temperatures.

As a result of the high strain rate sensitivity, the yield strength of SAC solders increases rapidly with strain rate. This increased yield strength suppresses any plastic deformation and prevents the shock energy from dissipating through the solder joint, thereby transferring more stress to the interface which causes interfacial fails. The yield strength of eutectic SnPb solder is relatively low compared to the SAC405 solder alloy. This means SnPb solders can dissipate more high strain rate energy through deformation and hence can perform better in shock than a SAC405 solder alloy. The higher yield strength of the SAC405 solder alloy is derived primarily from the precipitation hardening of the tin matrix by the Ag₃Sn precipitates/platelets. In addition to the increased bulk strength of the SAC alloy, the higher reflow temperatures can also cause an increased thickness in the IMC layers and thereby degrade the shock performance of the SAC405 solder alloy. However, the increased strength of the SAC405 solder alloy is beneficial for thermal cycle fatigue resistance as it reduces creep damage in each thermal cycle. Thus the transition from eutectic SnPb to SAC405 solder alloy poses more challenges in high strain rate shock applications, but provides more margin in thermal cycle reliability.

The LF fatigue performance was about 20-30% higher than SnPb for Flip Chip Ball Grid Array 9FCBGA (FCBGAs). Temperature cycle results are compared with the SnPb solder as shown in Figure 5. LF (SAC405) showed improved fatigue performance in both 15-min. and 30-min. dwell time testing.

Figure 5: LF temp cycle performance comparison with Sn/Pb solder
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LF creep performance concerns were addressed through long dwell time testing. Long dwell time temperature cycle testing (three cycles/day) were completed for SAC405, and the results showed better LF performance than SnPb solder as shown in Figure 6 [2].

Figure 6: LF Temp cycle performance in long dwell time testing
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The industry concern over long dwell time was satisfactorily addressed based on these results, and the LF reliability model correlation showed a similar type of fit compared to that of Sn/Pb solder. The corrosion and diffusion concerns were addressed through temperature humidity testing (85/85 test) and bake test (125°C) for 1000 hrs. Bake testing did not show interface-related failure mechanisms. The results are shown in Figure 7.

Figure 7: Bake test results for SAC405 with Im/Ag SF
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The other LF reliability concern is the formation of tin (Sn) whiskers. Sn whisker formation is not an issue for Pb-free solders, but concerns the Sn surface finish on components. The Sn whisker failure mechanism is an electrical short caused due to the growth of the whisker. An example of Sn whiskers is shown in Figure 8 [3].

Figure 8: Sn whiskers
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The concern about Sn whiskers for Sn-coated components is not related to LF issues, but it is the same as that for Sn/Pb solder. JSTD 201 was established for Sn whisker mitigation that includes the use of matte Sn and anneal at higher temperatures for stress relief prior to SMT.

PCB surface finish quality characteristics have an impact on reliability: micro void associated with Im/Ag PCB SF quality characteristics negatively impacted the solder fatigue margin (40-50% reduction in temperature cycle performance). The impact of micro void on temperature cycle performance is shown in Figure 9. The other concern is a Kirkendall-type void in bake testing for OSP SF. Kirkendall-type voids were attributed to Cu purity and OSP chemistry and are related to the coating process. Proper control of PCB plating quality mitigated the micro void risk for Im/Ag and Kirkendall-type void for OSP SF.

Figure 9: Impact of micro void on temperature cycle performance
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Pb-free Initiative: Surface-Mount Challenges

The transition to Pb-free solders for 2LI posed severe challenges to surface-mount technology, and an equivalent effort in adapting board manufacturing and SMT processes was required. The transition affected not just the SMT pastes used in board assembly, but also wave solders and board materials. Process steps significantly affected by the conversion are shown shaded in pink, with their impact described in Figure 10.

Figure 10: SMT process flow diagram indicating impact due to Pb-free transition
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Solder Paste Printing

The same stencil printing equipment, stencil fabrication technology, and stencil thickness used for SnPb can be used for Pb-free solder pastes. If reduced stencil aperture openings (when compared to the land area) are being used for SnPb pastes, these apertures will need to be expanded to cover the entire land area, since Pb-free solders do not wet out to the same extent as Pb-ed. The most popular Pb-free solder paste composition is SAC305.

Component Placement

Component placement is only marginally affected by the change to Pb-free solder. SAC solders are more grainy and less shiny than SnPb solders. There can also be a wider part-to-part variation in solder appearance. When front-side lighting is used for component lead or ball recognition, such as for BGAs, these differences may require adjustments to the vision system hardware and/or algorithms, to properly recognize Pb-free solder balls and surfaces.

Reflow Soldering

Since SAC305 has a higher initial melting point (217°C) than Sn-Pb (183°C), higher reflow soldering temperatures are required as shown in Figure 11. Wetting characteristics of SAC305 are not as superior as that of SnPb. This requires a slightly longer reflow soldering window, typically 230 to 250°C for Peak Reflow Temperature with 40 to 120 seconds above 217°C. Since this window is narrower than that used for eutectic SnPb, a greater level of control is required for Pb-free reflow soldering, and this necessitates better reflow soldering ovens. Ten zone ovens are typical for Pb-free reflow, instead of the seven zone ones sufficient for SnPb. Higher temperatures also lead to deleterious effects on the boards. Metallic surfaces not covered with solder paste during reflow soldering will get more oxidized than for SnPb, degrading the wetting of these surfaces during subsequent soldering processes, such as wave soldering. Using a nitrogen atmosphere in the reflow oven will mitigate this oxidation to a large extent. Higher reflow temperatures also increase PCB warpage, increase risk of delamination and blistering, and weaken the plated through-hole (PTH) copper. PCB laminates with higher glass transition temperatures, higher thermal degradation temperatures, longer time to delamination at temperatures at and above 260°C, as well as lower z axis expansion coefficients, will all help alleviate these issues.

Wave Soldering

SAC305 and eutectic SnCu are two alloys used for Pb-free wave soldering. Both have higher melting points (217°C and 227°C, respectively) than SnPb. Thus, an increased solder pot temperature is required, in the 260-275°C range, rather than the 250-260°C range. Increased temperatures may require a different wave solder flux, one that reaches an optimum activity level at a higher temperature. A new wave solder pot and machine are required to avoid cross-contamination between Pb-free and SnPb solders.

Figure 11: Comparison of peak reflow temperature ranges between eutectic SnPb (L) and SAC (R) alloys
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Since the Pb-free solders have diminished wettability under the same flux activity levels, filling PTHs to achieve strong reliable through-hole solder joints and adequate coverage of test point pads becomes a challenge, especially when using surface finishes such as OSP, which is prone to oxidation at higher temperatures. Examples of acceptable and unacceptable wave solder filling are shown in Figure 12. Some ways to mitigate these challenges are increasing flux application density, achieving adequate penetration of the flux in the through holes, and using a turbulent chip wave option. The latter, however, increases the dissolution and erosion of the copper lands and traces, and it also increases copper content in the solder pot. Since the melting points of Pb-free alloys increase quite markedly with an increase in the copper content, an effect that also reduces the fluidity of the solder wave, the copper content needs constant monitoring to avoid certain defects.

Figure 12: Unacceptable wave solder hole fill (L) and acceptable hole fill (R)
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In-Circuit Test (ICT)

Higher reflow and wave soldering temperatures cause two issues for In-Circuit Test (ICT). One, board test points collect extensive polymerized flux residue. This results in a larger build-up of this flux residue on test probe tips and barrels. Consequently, the test probes have to be cleaned more frequently in order to control retest rate increases caused by probe contamination. Two, there is increased oxidation of test points on the board. This results in higher contact resistance, which increases false failures, raising the retest rate and reducing the capacity of the test area. Probes with higher forces, sharper points, or rotating action can reduce the contact resistance issues with Pb-free boards, but can also cause board damage due to board flex and damage at test points. Using a nitrogen atmosphere during reflow and/or wave soldering can significantly reduce surface oxidation of the test points, but this will increase process costs. Also, because Pb-free solders are harder than SnPb, probe tips wear out faster, requiring more frequent replacement.

Solder Joint Inspection

SAC solder joints are typically less shiny and more grainy than eutectic SnPb joints as shown in Figure 13. SAC solder joints also spread less on lands and pads than SnPb joints. For these reasons, both manual and automated visual inspection criteria need to be adjusted for Pb-free board assemblies. Due to the lack of Pb, a heavy element, SAC solder has lower stopping power for x- rays. This causes x-ray images to appear a lighter shade of gray in transmission X-ray images used for inspection of solder joints that are not visible, such as BGA and QFN joints. Hence, Automated X-ray Inspection (AXI) criteria may also require adjustment.

Figure 13: Visual inspection difference between SnPb solder joint (L) and SAC solder joint (R)
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Rework

Repair and Rework become increasingly more difficult for Pb-free board assemblies, mainly due to the higher temperatures required for removing and replacing defective components. A greater amount of rework temperature control is required for Pb-free assemblies and this increases the total rework time in most cases. Due to the different solders, soldering irons and other equipment need to be changed from those used for SnPb rework. The risk of damage to the PCB lands, pads, and laminate is also increased, especially when there is direct contact between hotter soldering irons and the pads, such as during the Site Redressing process step for BGA component rework. Thinning of the copper thickness in the PTH barrel is significantly increased during the mini-pot rework process for connectors and other through-hole components as shown in Figure 14. The higher tin content of the SAC solders causes more copper dissolution and erosion, increasing barrel thinning. Use of newer Pb-free alloys can alleviate this copper dissolution/erosion to a large extent.

Figure 14: Copper erosion from minipot rework
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Pb-free Initiative: Customer Manufacturing Enabling Challenges

Given the significant challenges posed in the SMT materials and processes to enable Pb-free transition, an equivalent effort was needed to influence and enable the ODM and OEM customer base to adopt the Pb-free technologies and processes. The efforts undertaken by Intel to influence the industry are outlined in this section. Customer enabling for Pb-free board assembly consisted of multiple steps over four years prior to the July 2006 RoHS date.

1. A customer-ready document, informally called the Pb-free Manufacturing Advantage Service (MAS), was prepared to capture technical learnings from the Intel Lead Free Board Assembly Team (LFBAT). It included tutorial information on all Pb-free board assembly modules in a typical production line, and also the Intel Reference Process for each module, with detailed process parameters and process material selections. It served as a starting point for customer process development. The Pb-free MAS, containing a substantial wealth of information, was developed in order to meet customer's requirements for more detailed information.
2. Customer Manufacturing Enabling (CME), a new group at the time, engaged major ODM and OEM customers, delivered the Pb-free MAS in person (primarily in APAC), and invited certain customers to participate in further enabling activities.
3. One challenge with developing a board-level process was the limited availability of Pb-free boards and components. The CME team developed Pb-free test boards, with Pb-free Bills of Material (BOMs), representing designs from desktop, mobile, and server market segments. Selected customers in each segment were provided with board designs, or physical boards, and BOMs, or physical parts, depending on their preference.
4. Customers used the board kits (typically 75 boards) to develop a board assembly process on their own. Both Intel and customers then performed reliability tests on samples of the boards and shared results.
5. After results from the development builds were incorporated into customer processes, customers completed another round of builds with Intel representatives present, using additional Pb-free board kits. These were called validation builds, intended to confirm that the customer process could consistently produce good boards over a larger quantity (up to 200) in a manufacturing environment (rather than a lab), without tweaking the process mid-build. Again, Intel and customers separately performed reliability testing, Failure Analysis (FA), and Materials Analysis (MA) and again, shared results.
6. Intel and customers held Manufacturing Readiness Assessment meetings to review all results and customer status regarding their own further development work and builds of prototypes.
7. After the launch of Pb-free products, Intel monitored customer manufacturing performance during launch and ramp, providing assistance as needed.

By this process, Intel ensured a smooth launch and ramp for the initial Pb-free platforms in each segment. In addition, it helped drive industry convergence on a narrow set of Pb-free materials that allowed Intel to produce Pb-free components with only one ball alloy for all desktop, mobile, and server products.

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