Multi-Core Software

Process Scheduling Challenges in the Era of Multi-Core Processors

REFERENCES

[1] "Introducing the 45nm Next-Generation Intel® Core™ Microarchitecture," at http://www.intel.com/technology/architecture-silicon/intel64/
45nm-core2_whitepaper.pdf

[2] Nakajima, Jun and Pallipadi, Venkatesh, "Enhancements for Hyper-Threading Technology in the Operating System–Seeking the Optimal Scheduling," Workshop on Industrial Experiences with Systems Software, Boston, MA, Dec. 2002.

[3] R. Iyer, "CQoS: A Framework for Enabling QoS in Shared Caches of CMP Platforms," 18th International Conference on Supercomputing (ICS), San Malo, France, June 2004.

[4] Alexandra Fedorova, Margo Seltzer, Christopher Small and Daniel Nussbaum, "Performance Of Multithreaded Chip Multiprocessors and Implications For OS Design," in Proceedings of the USENIX 2005 Annual Technical Conference, Anaheim, CA, April 2005.

[5] Alexandra Fedorova, "Improving Performance Isolation on Chip Multiprocessors via an OS Scheduler," at http://www.eecs.harvard.edu/~fedorova/papers/fairsched.pdf

[6] "Moore's Law," at http://www.intel.com/technology/mooreslaw/index.htm

[7] "Intel® Centrino® Duo Processor Technology," at http://www.intel.com/products/centrino/duo/description.htm

[8] "Scheduling Domains," at http://lwn.net/Articles/80911/

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