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Volume 11, Issue 04

Multi-Core Software


Intel Technology Journal - Featuring Intel's recent research and development

ISSN 1535-864X DOI 10.1535/itj.1104.01

  • Volume 11
  • Issue 04
  • Published November 15, 2007

Multi-Core Software

  Section 11 of 12  

Integration Challenges and Tradeoffs for Tera–scale Architectures

REFERENCES

[1] Aart J.C. Bik, David Kreitzer, Xinmin Tian, "Compiler optimizations for the Intel® Core™2 Duo Processor," submitted to International J. of Parallel Programming, April 2007.

[2] Aart J.C. Bik, The Software Vectorization Handbook, Intel Press, Hillsboro, Oregon, 2004.

[3] A. Eichenberger, P. Wu, K. O'Brien, "Vectorization for SIMD Architectures with Alignment Constraints," in Proceedings of the ACM SIGPLAN 2004 Conference on Prog. Lang. Design and Implementation, pp. 82-93, Washington DC, June 2004.

[4] Intel Corporation, Intel Architecture Software Developer's Manual, Volume 1: Basic Architecture, Intel Corp. at http://developer.intel.com/design/index.htm, 2007.

[5] Andreas Krall and Sylvain Lelait, "Compilation Techniques for Multi-media Processors," International Journal of Parallel Programming, 28(4):347–361, 2000.

[6] Samuel Larsen and Saman Amarasinghe, "Exploiting Superword Level Parallelism with Multimedia Instruction Sets," in Proceedings of the SIGPLAN Conference on Programming Language Design and Implementation, Vancouver, B.C., June 2000.

[7] Steven Muchnick, Advanced Compiler Design and Implementation, Morgan Kaufmann Publishers, San Mateo, California, 1997.

[8] Ivan Pryanishnikov, Andreas Krall and Nigel Horspool, "Pointer Alignment Analysis for Processors with SIMD Instructions," in Proceedings of the 5th Workshop on Media and Streaming Processors, San Diego, CA, December 2003.

[9] John D. McCalpin, "Memory Bandwidth and Machine Balance in Current High Performance Computers," IEEE Computer Society Technical Committee on Computer Architecture TCCA, Newsletter, December 1995.

[10] Xinmin Tian, Milind Gikar, Aart J.C. Bik, and Hideki Saito, "Practical Compiler Techniques on Efficient Multithreaded Code Generation for OpenMP Programs," The Computer Journal, Vol. 48, Issue 5, pps. 558–601, 2005.

[11] Michael J. Wolfe, High Performance Compilers for Parallel Computing, Addison-Wesley, Redwood City, California, 1996.

[12] Somnath Ghosh, Abhay Kanhere, Rakesh Krishnaiyer, Dattatraya Kulkami, Wei Li, Chu-Cheow Lim, John Ng, "Integrating High-Level Optimizations in a Production Compiler: Design and Implementation Experience," in Compiler Construction, 12th International Conference, CC 2003: 303–319, Warsaw, Poland, April 2003.

  Section 11 of 12  

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