Tera-scale Computing

High-Performance Physical Simulations on Next-Generation Architecture with Many Cores

Yen-Kuang Chen, Corporate Technology Group, Intel Corporation
Jatin Chhugani, Corporate Technology Group, Intel Corporation
Christopher J. Hughes, Corporate Technology Group, Intel Corporation
Daehyun Kim, Corporate Technology Group, Intel Corporation
Sanjeev Kumar, Corporate Technology Group, Intel Corporation
Victor Lee, Corporate Technology Group, Intel Corporation
Albert Lin, Corporate Technology Group, Intel Corporation
Anthony D. Nguyen, Corporate Technology Group, Intel Corporation
Eftychios Sifakis, Corporate Technology Group, Intel Corporation
Mikhail Smelyanskiy, Corporate Technology Group, Intel Corporation

Index words: Physical simulations, chip multiprocessor, many cores, parallel scalability, memory bandwidth

Citation for this paper: Chen, Y.; Chhugani, J.; Hughes, C.; Kim, D.; Kumar, S.; Lee, V.; Lin, A.; Nguyen, A.; Sifakis, E.; Smelyanskiy, M. "High-Performance Physical Simulations on Next-Generation Architecture with Many Cores." Intel Technology Journal. http://www.intel.com/technology/itj/2007/
v11i3/8-simulations/1-abstract.htm (August 2007).

ABSTRACT

Physical simulation applications model and simulate complex natural phenomena. The computational complexity of real-time physical simulations far exceeds the capabilities of modern unicore microprocessors, which are limited to only tens of billions floating- point operations per second (FLOPS). However, the advent of multi-core architectures promises to soon make processors with trillions of FLOPS available. Such processors are also known as tera-scale processors. Physical simulations can exploit this huge increase in computational capability to increase realism, enable interactivity, and enrich a user's visual experience.

In this work, we study physical simulation applications in two broad categories: production physics and game physics. After parallelization, the benchmark applications achieve parallel scalabilities of 30x–60x on a simulated chip-multiprocessor with 64 cores.

We examine the memory requirements of physical simulation applications and find that they require cache sizes in excess of 128MB and main memory bandwidths in excess of hundreds of GB/s for real-time performance. A radical re-design of the memory hierarchy may be necessary for the multi-core tera-scale era to provide good scaling for this type of application.

Back to Top