Tera-scale Computing

Datacenter-on-Chip Architectures: Tera-scale Opportunities and Challenges

AUTHORS’ BIOGRAPHIES

Ravi Iyer
Ravi Iyer is a Principal Engineer with the Systems Technology Lab in Intel's Corporate Technology Group. His current research focus is on large-scale CMP architectures and technologies. Before joining STL, he held positions in the Communications Technology Lab (working on IO acceleration research) and in the Enterprise Products Group (working on server architecture and performance). He received his Ph.D. degree in Computer Science from Texas A&M University. He has filed 20+ patent applications and published 70+ papers in the areas of computer architecture, server design, network protocols/acceleration, workload characterization, and performance evaluation. He has held program committee member positions in various conferences and workshops (HPCA 2006, PACT 2007, IISWC 2007, etc.). He is also an Associate Editor for IEEE Transactions on Parallel and Distributed Systems (IEEE TPDS) and is currently guest co-editor for a special issue on CMP architectures. His e-mail is ravishankar.iyer at intel.com.

Ramesh Illikkal
Ramesh Illikkal is a Senior Researcher in the Systems Technology Lab at Intel. His research interests are in CMP, server architectures, virtualization, and memory hierarchies. He received his Masters degree in Electronics from Cochin University of Science and Technology. His e-mail is ramesh.g.illikkal at intel.com.

Li Zhao
Li Zhao received her Ph.D. degree in Computer Science from the University of California, Riverside. She is currently a Senior Engineer in the Systems Technology Laboratory at Intel. Her research interests include computer architecture, network computing, and performance evaluation. She is a member of the IEEE. Her e-mail is li.zhao at intel.com.

Srihari Makineni
Srihari Makineni is a Senior Researcher in the Systems Technology Lab at Intel. He has been working at Intel for more than 11 years. His research interests include cache/memory subsystems, interconnects, networking, and large-scale CMP architectures. Makineni received an M.S. degree in Electrical and Computer Engineering from Lamar University, Texas. His e-mail is srihari.makineni at intel.com.

Don Newell
Don Newell is a Senior Principal Engineer in the Systems Technology Lab at Intel. His research interests include server architecture, networking, and I/O acceleration. Newell received a B.S. degree in Computer Science from the University of Oregon. His e-mail is donald.newell at intel.com.

Jaideep Moses
Jaideep Moses is a Senior Engineer in the Systems Technology Lab at Intel. Prior to this, Jaideep worked in the Communication Technology Lab on I/O acceleration research. He also worked in the former Enterprise Products Group focusing on modeling, simulation, and analysis of platform architecture and design including simulation-based verification of a coherence protocol. His current research focus is on large-scale CMP platform architecture analysis and design. Jaideep received his M.S. degree in Computer Science from the University of Texas at El Paso. His e-mail is jaideep.moses at intel.com.

Padma Apparao
Padma Apparao is a Senior Researcher in the Systems Technology Lab at Intel. Padma received her Ph.D. degree from the University of Florida and has been working on performance analysis of server workloads. Her current research interest is in the areas of virtualization and large-scale CMP architecture analysis. Her e-mail is padmashree.k.apparao at intel.com.

Note: The use of SPEC or TPC benchmark configurations and traces in this paper is purely for analysis and illustration. They are not intended to provide any indication of performance of a specific platform.

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