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Volume 11, Issue 03

Tera-scale Computing


Intel Technology Journal - Featuring Intel's recent research and development

ISSN 1535-864X DOI 10.1535/itj.1103.06

  • Volume 11
  • Issue 03
  • Published August 22, 2007

Tera-scale Computing

  Section 7 of 8  

Datacenter-on-Chip Architectures: Tera-scale Opportunities and Challenges

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[3] "Xen Virtualization Technology," Xen Source, at http://www.xensource.com/*

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[7] Intel Corporation, "Tera-scale Computing," at http://techresearch.intel.com/articles/Tera-Scale/1421.htm

[8] Intel Corporation, "Intel® Xeon® Processor 5000 Sequence," at http://www.intel.com/products/processor/xeon5000/index.htm?
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[9] R. Iyer, "On Modeling and Analyzing Cache Performance using CASPER," Int'l Symposium on Modeling, Analysis and Simulation of Computer & Telecom Systems, Oct. 2003.

[10] R. Iyer, "CQoS: A Framework for Enabling QoS in Shared Caches of CMP Platforms," 18th Annual International Conference on Supercomputing (ICS'04), July 2004.

[11] R. Iyer, L. Zhao, et al., "QoS Policies and Architecture for Cache/Memory in CMP Platforms," SIGMETRICS, 2007.

[12] C. Kim, D. Burger, S. W. Keckler, "Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches," IEEE Micro 23(6), pp. 99–107, 2003.

[13] S. Kim, D. Chandra, and Y. Solihin, "Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture," 13th Int'l Conf. on Parallel Arch. & Complication Techniques (PACT), Sept. 2004.

[14] K. Lauritzen, T. Sawicki, et al., "Intel® I/O Acceleration Technology Improves Network Performance, Reliability and Efficiently," Technology@Intel Magazine.

[15] C. Liu, A. Sivasubramaniam, and M. Kandemir, "Organizing the Last Line of Defense before Hitting the Memory Wall for CMPs," 10th IEEE Symposium on High-Performance Computer Architecture, Feb. 2004.

[16] K. Nesbit, et al., "Fair Queuing Memory Systems," in Proceedings. of Annual International Symposium on Microarchitecture (MICRO), June 2006.

[17] K. Nesbit, et al., "Virtual Private Caches," International Symposium on Computer Architecture (ISCA), June 2007.

[18] M. K. Qureshi and Y. N. Patt, "Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches," Int'l Symposium on Microarchitecture (MICRO), June 2006.

[19] M. Qureshi, A. Jaleel, et al., "Adaptive Insertion Policies for High Performance Caching," International Symposium on Computer Architecture (ISCA), June 2007.

[20] N. Rafique, W.T. Lim and M. Thottethodi, "Architectural Support for Operating System-Driven CMP Cache Management," Int'l Conference on Parallel Architectures and Compilation Technology (PACT 2006), Sept. 2006.

[21] P. Ranganathan and N. Jouppi, "Enterprise IT Trends and Implications on Architecture Research," 11th Int'l Symp. on High Performance Computer Architecture (HPCA), 2005.

[22] G. Regnier, S. Makineni, R. Illikkal, R. Iyer, et al., "TCP Onloading for Datacenter Servers," IEEE Computer, 2004.

[23] M. Rosenblum and T. Garfinkel, "Virtual Machine Monitors: Current Technology and Future Trends," IEEE Transactions on Computers, 2005.

[24] Sap America Inc., "SAP Standard Benchmarks," at http://www.sap.com/solutions/benchmark/index.epx*

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[26] SPECjbb2005, at http://www.spec.org/jbb2005/*

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[29] TPC-W Benchmark, at www.tpc.org/tpcw/*

[30] TPC-W Publication, at http://www.tpc.org/results/FDR/tpcw/
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*

[31] VMware Corporation, Server Consolidation and Containment with VMware Virtual Infrastructure, at http://www.vmware.com/pdf/server_consolidation.pdf*

[32] R. Uhlig, et al., "Intel Virtualization Technology," IEEE Transactions on Computers, 2005.

[33] T. Deshane, D. Dimatos, et al., "Performance Isolation of a Misbehaving Virtual Machine with Xen, VMware and Solaris," at http://people.clarkson.edu/~jnm/publications/
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[34] T. Y. Yeh and G. Reinman, "Fast and Fair: Data-stream Quality of Service," Int'l Conf. of Compilers, Architecture and System For Embedded Systems (CASES), July 2004.

[35] M. Zhang and K. Asanovic, "Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors, 32nd International Symposium on Computer Architecture (ISCA-32), Madison, 2005.

[36] L. Zhao, R. Iyer, et al., "Performance, Area and Bandwidth Implications on Large-Scale CMP Cache Design," Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI), Feb. 2007.

[37] L. Zhao, R. Iyer, et al., "CacheScouts: Fine-Grain Monitoring of Shared Caches in CMP Platforms," to appear in 16th International Conference on Parallel Architectures and Compilation Techniques (PACT), Sept. 2007.

  Section 7 of 8  

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