Tera-scale Computing

Package Technology to Address the Memory Bandwidth Challenge for Tera-scale Computing

REFERENCES

[1] Held, J., Bautista, J. and Koehl, S., "From a Few Cores to Many: A Tera-scale Computing Research Overview," Research at Intel White Paper, http://download.intel.com/research/platform/terascale/
terascale_overview_paper.pdf, 2006.

[2] Hsu, L., Iyer, R., Makineni, S., Reinhardt, S. and Newell, D., "Exploring the Cache Design Space for Large Scale CMPs," ACM SIGARCH Computer Architecture News, vol. 33, no. 4, Sept. 2005, pp. 24–33.

[3] Mallik, D. Radhakrishnan, K., He, J., Chiu, C., Kamgaing, T., Searls, D. and Jackson, J. D., "Advanced Package Technologies for High-Performance Systems," Intel Technology Journal, vol. 9, no. 4, Nov. 9, 2005, pp. 259–271.

[4] Moore, S. K., "Winner: Masters of Memory," IEEE Spectrum, Jan. 2007, pp. 45–49.

[5] Patti, R., "Design and Application of 3D Memories," Proceedings of IMAPS International Conference and Exhibition on Device Packaging, Feb. 27, 2007.

[6] Vangal, S., et al., "An 80-Tile 1.28TFLOPS Network-on-Chip in 65 nm CMOS," in Proceedings of ISSCC 2007 (IEEE International Solid-State Circuits Conference), Feb. 12, 2007.

[7] Johnson, R. C., "Intel's Teraflops Chip Uses Mesh Architecture to Emulate Mainframe," EE Times Online, at http://www.eetimes.com/showArticle.jhtml?articleID=197004697*, Feb. 12, 2007.

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