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Volume 11, Issue 03

Tera-scale Computing


Intel Technology Journal - Featuring Intel's recent research and development

ISSN 1535-864X DOI 10.1535/itj.1103.03

  • Volume 11
  • Issue 03
  • Published August 22, 2007

Tera-scale Computing

  Section 7 of 10  

Package Technology to Address the Memory Bandwidth Challenge for Tera-scale Computing

SUMMARY AND CONCLUSION

Memory bandwidth is one of the key challenges associated with tera-scale computing. Package technology will play a key role in answering that challenge. In this paper, we reviewed the historical trends in memory bandwidth and their impact on package technology. Key challenges in the past have been a continuing pin count growth that leads to package body size growth as well as design challenges. In addition, there are fundamental limits to the off-package memory bus speed that can be supported. A transition to on-package memory is necessary for supporting tera-scale computing needs. We reviewed a transitional, evolutionary roadmap for package technology to implement on-package memory architectures capable of meeting the needs of tera-scale computing. Table 2 summarizes the technology and architecture options, features, capabilities, and limits of each.

Table 2: Summary of features and capabilities of on-package memory architectures
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  Section 7 of 10  

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