Tera-scale Computing

Package Technology to Address the Memory Bandwidth Challenge for Tera-scale Computing

TERA-SCALE COMPUTING MEMORY BANDWIDTH CHALLENGES FOR PACKAGE TECHNOLOGY

Figure 6 shows the historical trend for memory bandwidth demand [3]. Today's bandwidth demand is in the 10-20GB/s range. From Figure 4 it is obvious that the move to multi- and many-core computing will easily drive a need for bandwidth in the 100s GB/s range in the not so distant future. Extrapolating from this, a target of 1TB/s of memory bandwidth for tera-scale computing architectures is not unreasonable [3–5].

Figure 6: Historical trend for memory bandwidth [3]
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Re-architecting a system capable of delivering this level of bandwidth is a challenge, given that the traditional methods are already reaching realistic limits. On many microprocessors, SRAM already occupies approximately half of the die real estate [4]. Increasing the amount of on-die memory becomes prohibitive from a cost and die size growth perspective. Increasing the bandwidth of board-level memory becomes prohibitive because of the continued increase in pin count and power with interconnect speed required to sustain bandwidth increases. Using on-package memory becomes a potential attractive intermediary level in the memory hierarchy that can work with chip-level and board-level memory to provide the bandwidth for tera-scale computing applications.

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