Tera-scale Computing

Package Technology to Address the Memory Bandwidth Challenge for Tera-scale Computing

REVIEW OF PACKAGE TECHNOLOGY EVOLUTION VS. MEMORY BANDWIDTH REQUIREMENTS

In the traditional system architecture of Figure 1, the packaging challenges associated with ever-evolving and increasing memory bandwidth impacted both chipset and CPU packaging. The chipset package has usually absorbed the need for increasing numbers of connections to system memory, while the CPU packaging dealt primarily with the need for an interconnect that could support increases in the system bus speed. Two almost simultaneous system architecture transitions are collapsing the focus of the memory bandwidth packaging challenges to primarily CPU packaging.

The first transition is the transition to an Integrated Memory Controller (IMC) in the CPU. Figure 3 illustrates the shift in the system architecture from that of Figure 1. The system memory now interfaces directly to the CPU through a system memory bus. The entire burden of pin count and interconnect speed to sustain increases in memory bandwidth requirements now falls on the CPU package alone.

Figure 3: System architecture with integrated memory controller on the CPU
click image for larger view
 

The second system architecture transition is the potential move to multi- and many-core CPU architectures. With the increase in cores comes a dramatic transition in memory bandwidth to "feed" the cores, particularly for the class of parallel applications envisioned. Since the CPU package is now the primary interconnect to the system memory, the CPU package bears the burden of the increase in memory bandwidth. Figures 4 and 5 illustrate the transition in memory bandwidth requirements and the projected CPU package pin count growth, respectively, as the transition to multi- and many-core CPUs with integrated memory controllers occurs.

Figure 4: Bandwidth requirements
click image for larger view
 

Figure 5: Package pin count growth for memory I/Os
click image for larger view
 

One solution to address the bandwidth challenge and to stave off the continued increase in package pin count is to incorporate memory into a CPU + Memory Multichip Package (MCP). This changes the paradigm of packaging and the role of packaging in the memory hierarchy. Whereas packaging has previously been an enabler of higher bandwidths, now packaging would become a crucial sub-level in the overall memory system hierarchy. Moving to on-package memory, however, is not a trivial solution to implement. In the final main section of this paper, we discuss the challenges and benefits/capabilities of an MCP configuration and various MCP architectures. First it is beneficial to discuss tera-scale computing challenges in the area of memory bandwidth.

Back to Top