Tera-scale Computing

Package Technology to Address the Memory Bandwidth Challenge for Tera-scale Computing

AUTHORS’ BIOGRAPHIES

Lesley Anne Polka
Lesley Anne Polka joined Intel in 1994. She is a Staff Electrical Packaging Engineer and works in the Assembly and Test Technology Development Division in Chandler, Arizona. Her focus is electrical issues related to development of Intel's packaging technologies for CPU, chipset, and wireless/RF packaging. During her twelve and a half years at Intel she has worked on various aspects of electrical packaging, including high-speed I/O and signal integrity, power delivery, analysis and characterization. She is presently working on new CPU package architectures to meet memory bandwidth and power-delivery challenges for future Intel microprocessors. Lesley has published over 15 papers on topics related to electrical design and technology development for microprocessor packaging and computational electromagnetics. She has two U.S. patents in packaging and a third U.S. patent pending in this area. Lesley obtained her B.S., M.S. and Ph.D. degrees, all in Electrical Engineering, from Arizona State University, in 1987, 1989 and 1995, respectively. Her e-mail is lesley.a.polka at intel.com.

Huthasana (Huthas) Kalyanam
Huthasana (Huthas) Kalyanam has been with Intel Corporation for the past one and a half years. He works as a Packaging Engineer within the Design Group in the Assembly and Test Technology Development Division in Chandler, Arizona. His primary job responsibilities include designing packages that are optimized for cost, electrical performance, and form factor. He designs packages that cater to Intel's Server and Desktop market segments. His responsibilities also include designing test packages for Intel's next-generation path-finding efforts in Packaging and Silicon. He is currently working on designing packages for multichip designs. Huthas received his M.S. degree in Electrical Engineering with a focus on VLSI and Analog systems from the University of Colorado at Boulder in 2004, after which he worked for a year with Instec Inc. Boulder as a Product and Design Engineer for Instec's Embedded Systems. His e-mail is huthasana.kalyanam at intel.com.

Grace Hu
Grace Hu joined Intel in 2005 as an Electrical Packaging Engineer. She works on high-speed I/O characterization for CPU and chipset packages. Her focus areas also include high-frequency measurement and metrology development, broad-band dielectric material characterization, and risk assessments for new package technologies. Grace obtained her B.S. degree from Shanghai Jiao Tong University and her M.S. degree from the University of Missouri-Rolla, both in Electrical Engineering in 1999 and 2002, respectively. Her e-mail is grace.hu at intel.com.

Satish Krishnamoorthy
Satish Krishnamoorthy joined Intel in 2005 and works as an Electronic Packaging Engineer in the Assembly and Test Technology Development Division at Chandler, Arizona. His focus is in package electrical analysis and design with particular emphasis on power delivery and signal integrity for various CPU and chipset products. Satish has published over five papers in refereed journals in the area of electronic circuits. He obtained his B.S. degree in Electronics and Communication Engineering from Anna University and his M.S. degree in Electrical Engineering from Arizona State University, in 2003 and 2005, respectively. His e-mail is satish.krishnamoorthy at intel.com.

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