Tera-scale Computing

Package Technology to Address the Memory Bandwidth Challenge for Tera-scale Computing

Lesley Anne Polka, Assembly and Test Technology Development Division, Intel Corporation
Huthasana Kalyanam, Assembly and Test Technology Development Division, Intel Corporation
Grace Hu, Assembly and Test Technology Development Division, Intel Corporation
Satish Krishnamoorthy, Assembly and Test Technology Development Division, Intel Corporation

Index words: package technology, memory bandwidth, package design, electrical performance

Citation for this paper: Hu, G.; Kalyanam, H.; Krishnamoorthy, S.; Polka, L. "Package Technology to Address the Memory Bandwidth Challenge for Tera-scale Computing." Intel Technology Journal. http://www.intel.com/technology/itj/2007/
v11i3/3-bandwidth/1-abstract.htm (August 2007).

ABSTRACT

Tera-scale computing stresses the platform architecture with memory bandwidth being a likely bottleneck to processor performance that presents unique challenges to CPU packaging. This paper describes the evolution in packaging technology with each processor generation to meet increasing memory bandwidth needs and the revolution in package technology required for tera-scale computing needs. The scope and focus of the paper are primarily design and electrical performance challenges. We discuss a potential roadmap of transitions in package architecture and technology that evolves from today's off-package memory scenario to increasingly complex on-package integrated memory architectures. An overall treatment of memory hierarchy, including off-die memory approaches, is not within the scope of this paper, but relevant to the overall challenge of enabling higher bandwidth. Again, the focus of this paper is on the CPU package itself. In this context, we discuss the memory bandwidth limitations, technology challenges, and tradeoffs of each package architecture.

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