- Home›
- Technology and Research›
- Intel Technology Journal›
- Tera-scale Computing
Tera-scale Computing
Accelerator Exoskeleton
Perry Wang,
Corporate Technology Group, Intel Corporation
Jamison Collins,
Corporate Technology Group, Intel Corporation
Gautham Chinya,
Corporate Technology Group, Intel Corporation
Hong Jiang,
Mobility Group, Intel Corporation
Xinmin Tian,
Software Solutions Group, Intel Corporation
Milind Girkar,
Software Solutions Group, Intel Corporation
Lisa Pearce,
Mobility Group, Intel Corporation
Guei-Yuan Lueh,
Mobility Group, Intel Corporation
Sergey Yakoushkin,
Corporate Technology Group, Intel Corporation
Hong Wang,
Corporate Technology Group, Intel Corporation
Citation for this paper: Chinya, G.; Collins, J.; Girkar, M.; Jiang, H.; Lueh, G.; Pearce, L.; Tian, X.; Wang, H.; Wang, P.; Yakoushkin, S. "Accelerator Exoskeleton." Intel Technology Journal.
http://www.intel.com/technology/itj/2007/
v11i3/2-exoskeleton/1-abstract.htm (August 2007).
ABSTRACT
To maximize performance and power efficiency, future multi-core architectures may be heterogeneous, incorporating some accelerator cores alongside the IA cores. Accelerator Exoskeletons provide a shared virtual memory heterogeneous multi-threaded programming paradigm for these accelerators using novel CPU instruction set extensions and software tool chains with an Intel® Architecture (IA) look-n-feel. Firstly, we introduce the proposed architectural extensions known as the Exoskeleton Sequencer (EXO), which represents heterogeneous accelerators as ISA-based MIMD architecture resources, and a shared virtual memory heterogeneous multi-threaded program execution model that tightly couples specialized accelerator cores with general-purpose CPU cores. Then we introduce the C for Heterogeneous Integration (CHI) programming environment that includes a compiler, runtime, debugger, and performance-analysis tools. The CHI compiler extends the OpenMP pragma for heterogeneous multi-threading programming, and it produces a single fat binary with code sections corresponding to different instruction sets. The runtime can judiciously spread parallel computation across the heterogeneous cores to optimize performance and power.
