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Volume 11, Issue 03

Tera-scale Computing


Intel Technology Journal - Featuring Intel's recent research and development

ISSN 1535-864X DOI 10.1535/itj.1103.01

  • Volume 11
  • Issue 03
  • Published August 22, 2007

Tera-scale Computing

  Section 9 of 10  

Integration Challenges and Tradeoffs for Tera–scale Architectures

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[11] P. Gratz, K. Sankaralingam, H. Hanson, P. Shivakumar, R. McDonald, S. Keckler, D. Burger, "Implementation and Evaluation of a Dynamically Routed Processor Operand Network," IEEE/ACM International Symposium on Networks–on–Chips (NOCS), May 2007.

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[17] D. Lenoski, J. Laudon, T. Joe, D Nakahira, L Stevens, A. Gupta, and J. Hennessy, "The DASH Prototype: Implementation and Performance," In Proceedings19th International Symposium on Computer Architecture, pp. 92–103, Gold Coast, Australia, May 1992.

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[25] M. B. Taylor, W. Lee, S. Amarasinghe, A. Agarwal, "Scalar Operand Networks: On-chip Interconnect for ILP in Partitioned Architectures," International Symposium on High Performance Computer Architecture, February 2003.

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[27] S. Vangal et al., "An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS," IEEE International Solid-State Circuits Conference, Feb. 2007.

[28] H–S. Wang, L-S. Peh, N. Jha, "Power-driven design of router microarchitectures in on-chip networks," International Symposium On Microarchitecture (MICRO'03), pp. 105–116, Nov. 2003.

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[30] M. Zhang and K. Asanovic, "Victim Migration: Dynamically Adapting Between Private and Shared CMP Caches," MIT CSAIL Technical Report, MIT-CSAIL-TR-2005-064, Cambridge, MA, October 2005.

[31] M. Zhang and K. Asanovic, "Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors," in Proceedings 32nd International Symposium on Computer Architecture, Madison, WI, June 2005.

  Section 9 of 10  

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