Tera-scale Computing

Integration Challenges and Tradeoffs for Tera-scale Architectures

ARCHITECTURAL VISION

The tera-scale architectural vision, as shown in Figure 1, takes the integration trend to its logical progression by consolidating not only a large number of general-purpose computing cores but also special-purpose computing engines (e.g., texture units, shader units, fixed function units), and platform elements, such as memory and I/O controllers, in a single die. A tera-scale processor may also include a system interface to allow multiple such processors to connect with each other and with other system peripherals.

FFU: Fixed Function Unit, Mem C: Memory Controller, PCI-E C: PCI-based Controller, R: Router, ShdU: Shader Unit, Sys I/F: System Interface, TexU: Texture Unit

Figure 1: Tera-scale architecture: high-level block diagram
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The tera-scale architecture uncore consists of the following key elements:

• A scalable high-bandwidth, low-latency, and power-efficient interconnect to connect the computing and platform elements together and allow them to exchange information with each other, access memory, and communicate with the rest of the system.
• A cache hierarchy that allows the multiple computing elements to effectively utilize and share the on-die memory resources.
• A scalable, high-bandwidth memory architecture that can effectively feed the large number of computing elements.

We expect tera-scale processors to be highly optimized for specific market segments through variations in the number of computing engines, by having different types of fixed function blocks, and having a different type and number of memory and I/O resources. Not all building blocks require the high bandwidth and low latency offered by the scalable interconnect. We expect blocks that are not candidates for integration into the main interconnect and cache hierarchy to be attached to auxiliary interconnects suitable for specific needs.

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