Tera-scale Computing

Integration Challenges and Tradeoffs for Tera-scale Architectures

AUTHORS’ BIOGRAPHIES

Mani Azimi
Mani Azimi is a Senior Principal Engineer and Director of the Platform Architecture Research team in the Microprocessor Technology Laboratory in Intel's Corporate Technology Group. He received his Ph.D. degree from Purdue University. He joined Intel in 1990 and has worked on a wide range of platform architecture topics including system protocol, processor interface, MP cache controller architecture, and performance modeling/analysis. He is currently focusing on tera-scale computer architecture challenges. His e-mail is mani.azimi at intel.com.

Naveen Cherukuri
Naveen Cherukuri is a research scientist in Microprocessor Technology Labs at Intel Corporation, Santa Clara, California. He is currently a lead investigator of cache architecture and microarchitecture for Intel’s Tera-scale Microprocessors. Earlier, he was a member of Itanium processor design team with direct responsibility for bus timing and signal integrity, power delivery and package design. Prior to joining Intel, he was involved in the design and marketing of multichip modules at Fujistu Microelectronics in San Jose, CA. Naveen holds an MSEE from the University of Arizona, Tucson, Arizona. He can be reached at naveen.cherukuri at intel.com.

D. N. Jayasimha
D. N. Jayasimha is a Principal Engineer in the Corporate Technology Group at Intel Corporation with research interests in multiprocessor architectures, interconnects, and performance analysis. Prior to joining Intel he was a faculty member in Computer Science at the Ohio State University. He received his Ph.D. degree from the University of Illinois at Urbana Champaign. His e-mail is jay.jayasimha at intel.com

Akhilesh Kumar
Akhilesh Kumar is a Principal Engineer in Intel's Corporate Technology Group and leads the definition of protocols for on–chip and off-chip system interconnects. His research interests include cache organization, on–chip and off–chip interconnects, and interface protocols. He received his Ph.D. degree in Computer Science from Texas A&M University. His e-mail is akhilesh.kumar at intel.com.

Partha Kundu
Partha Kundu is a Senior Staff Research Scientist within Intel's Microprocessor Technology Labs (MTL) in Santa Clara, California. He was an architect of the Intel^® Itanium^® architecture and a Principal Architect on a DEC/Alpha microprocessor. His research interests include on-chip networks, memory system design, transactional memory, and performance simulation. He holds an M.S. degree from the State University of New York, Stony Brook. His e-mail is partha.kundu at intel.com.

Seungjoon Park
Seungjoon Park is a Research Scientist within Intel's Microprocessor Technology Labs (MTL) in Santa Clara, California. At Intel, he has contributed to the definition and formal verification of off-die and on-die cache coherence and system interface protocols. Prior to Intel, he worked at NASA Ames Research Center with the High-Assurance Software Design Research team on Java PathFinder, a system to verify executable Java bytecode programs. He received his Ph.D. degree in Electrical Engineering with a Minor in Computer Science from Stanford University, where he investigated the cache coherence protocol of the Stanford FLASH multiprocessor and developed operational memory models of SPARC V9 architecture.

Ioannis (Yannis) Schoinas
Ioannis (Yannis) Schoinas is a Principal Engineer in Intel's Corporate Technology Group. He received his B.S. and M.S. degrees from the University of Crete-Heraclion and his Ph.D. degree from the University of Wisconsin-Madison. At Intel he has worked on a wide range of platform architecture topics including coherence protocol, memory RAS, system partitioning, configuration management, system security, and virtualization. He is currently focusing on tera-scale computer architecture challenges. His e-mail is ioannis.t.schoinas at intel.com.

Aniruddha S. Vaidya
Aniruddha S. Vaidya is a Research Scientist at Intel's Microprocessor Technology Labs (MTL) in Santa Clara, California. His contributions at Intel include workload characterization, performance analysis, and architecture of server platforms. His current focus is on router and interconnection network architecture for Intel's tera-scale computing initiative. Ani has B.Tech and M.Sc. (Engg.) degrees from Banaras Hindu University and the Indian Institute of Science, and a Ph.D. degree in Computer Science and Engineering from the Pennsylvania State University. His e-mail is aniruddha.vaidya at intel.com.

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