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Tera-scale Computing
Integration Challenges and Tradeoffs for Tera-scale Architectures
Mani Azimi,
Corporate Technology Group, Intel Corporation
Naveen Cherukuri,
Corporate Technology Group, Intel Corporation
D. N. Jayasimha,
Corporate Technology Group, Intel Corporation
Akhilesh Kumar,
Index words: tiled architecture, on-die interconnect, cache hierarchy, communication protocol
Citations for this paper. Azimi, M.; Cherukuri, N.; Jayasimha, D.N.; Kumar, A.; Kundu, P.; Park, S.; Schoinas, I.; Vaidya, A. "Integration Challenges and Tradeoffs for Tera-scale Architectures." Intel Technology Journal.
http://www.intel.com/technology/itj/2007/
v11i3/1-integration/1-abstract.htm (August 2007).
ABSTRACT
Tera-scale processors promise to offer an unprecedented concentration of computing power and enable novel usages and applications. The computing power may be provided by a combination of general-purpose cores and special-purpose (fixed or programmable) computing engines. Further, Moore's law enables the integration of additional system resources to the processor die. However, the realization of tera-scale architecture is challenged by on-die power dissipation, wire delays, off-chip memory bandwidth, process variations, and higher failure rates. These challenges create opportunities for architectural innovation. One of the ways to address these challenges is through the use of a "tiled" architecture: the die is divided into a large number of identical or close-to-identical, tiles that are interconnected using a scalable and energy-efficient interconnect. This modular approach enables ease of layout and rapid integration of different blocks. Limited off-chip memory bandwidth requires innovations in the cache hierarchy, memory subsystem, and coherence protocol. We present an architectural vision for the tera-scale processors and discuss the performance, scalability, and manufacturability aspects of the uncore. We articulate key challenges and point to candidate solutions for these challenges.
