Technology innovation and technology leadership are not possible for technology companies without a never-ending attention to risk and its management. Using Moore's Law as a roadmap, we, at Intel, need to translate the roadmap into innovative products for the market place and to manage the risk associated with product innovations. This includes both processor microarchitecture innovation and silicon process innovations; both of which go hand in hand. We have developed a model to minimize the risk associated with the introduction of new silicon processes and microarchitectures by alternating our focus. This cadence between microarchitecture and the silicon cycle is referred to as the "tick-tock" model [1]. The term "tick-tock" comes from the steady recurrent ticking sound made by a clock. Each "tick" represents the silicon process beat rate, which has a corresponding "tock" representing the design of a new microarchitecture delivered in a cycle approximately every two years. This model minimizes the risk associated with the introduction of new silicon processes and microarchitectures by alternating the focus from silicon to microarchitecture.

This Intel Technology Journal (Vol. 11, Issue 2) on "The Spectrum of Risk Management in a Technology Company" takes an intriguing look at a myriad of risk management techniques used at Intel Corp. The first four papers look at the risk associated with the technology treadmill such as those encountered with technological advances; what competitors are doing; and what the marketplace wants. The second group of four papers looks at risk in daily business execution.

The first paper examines risk associated with advanced technology important in the supply chain. It examines a case study on applying strategic bets in the lithographic supply chain. A system was developed to assess technical and business risk for all components of the supply chain. Then a methodology for identifying fellow travelers, including consortia, was used to create programs to establish a foundation of common technologies such as extreme ultra-violet lithography. The second paper looks at managing product development risk through the implementation of a six-step active risk management process and tool. The process provides a consistent language and approach to measuring risk. The tool provides risk visibility despite the many-to-many relationships that exist between Intel ingredients and platforms to avoid potential costly risk events. Monte Carlo simulations are used.

The third paper in this Intel Technology Journal (Vol. 11, Issue 2) looks at acquisition risk for managing goods and services. We describe three specific risk mitigation techniques: Internet negotiations, escrow accounts, and currency risk reduction to reduce exposure to universal business risks. The fourth paper looks at demand forecasting. Demand risk is implicit to manufacturing businesses, but for high-tech firms it poses a particularly strong threat. As product lifecycles shrink and new generations of technology enter the market more quickly, achieving strong top- and bottom-line results hinges on estimating overall demand and product mix as accurately as possible. We propose using Information Aggregation Mechanisms (IAMs) to address demand risk and other business challenges by improving organizational information flow. Based on results to date, our IAM implementations appear to have had a desirable impact on forecast accuracy and stability.

The next group of four papers looks at risk in daily business execution. The fifth paper reviews doing business appropriately around the globe. Intel has business and manufacturing locations around the world. This paper describes the complexities of maintaining Intel's business activities in restricted countries including maintaining regulatory compliance, adhering to security guidelines, protecting Intel's intellectual property, and employment. Intel must comply with United States and international law without impeding Intel's growth and continued success in these countries. The sixth paper provides an overview of the major environmental, health, and safety risks that apply to semiconductor manufacturing and what specific approaches are used to assess and reduce the risks in each new generation of facility or semiconductor fabrication process. We show how a systems approach that ties all risks together has helped Intel manage these risks despite significant changes in process and facilities design over the last ten years.

The seventh paper looks at managing loss due to hazard risks which include perils such as fire, explosions, floods, windstorms, earthquakes and typhoons. This paper describes Intel's risk management process for the identification, analysis, and control of hazard loss risks. The eight and final paper examines business continuity process in the supply chain. In order to reliably produce quality products, Intel needs to be able to quickly react to a crisis, ensure continuity of our business, and restore the supply chain. Intel's business continuity methodology, infrastructure, and tools used within Intel's Materials organization have improved Intel's ability to quickly recover from a supply chain outage and restore supply to manufacturing and other operations.

We at Intel Corporation have unique risks as a leading computer company. Our manufacturing environments, which are ultra-clean, pristine fabrication facilities with sensitive, specialized high-value equipment, producing high volumes of product at nano-width geometries with uncompromising quality in of itself creates many challenges. Our abilities to assess, manage and react to risk associated with technology treadmill and everyday business is what keeps Intel at the forefront of our business.

Reference:

[1] Shenoy, Sunil and Daniel, Akhilesh, Intel^® Architecture and Silicon Cadence: The Catalyst for Industry Innovation, Technology at Intel Magazine, 2006, October.