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Volume 11, Issue 02
The Spectrum of Risk Management in a Technology Company
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Technology and Research   Intel Technology Journal  
ITJ The Spectrum of Risk Management in a Technology Company
 Intel Technology Journal - Featuring Intel's Recent Research and Development
The Spectrum of Risk Management in a Technology Company
Volume 11    Issue 02    Published May 16, 2007
ISSN 1535-864X    DOI: 10.1535/itj.1102
Foreword
Foreword
By Karl Kempf
Fellow and Director of Decision Technologies
Technology and Manufacturing Group, Intel Corporation
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Current Articles
Risk on the Technology Treadmill
Managing New Technology Risk in the Supply Chain
Take a look at key Intel strategies to manage new technology risks and learn about the fine line that has to be drawn between overinvestment in research that might compromise product margins and underinvestment that might cause Intel to miss a technology node.
Managing Product Development Risk
In today's world, with increased competition, and ever more demanding usage models it is imperative to have a risk management process that helps Intel successfully deliver to the market. Our authors examine Intel's product development risk process and show how its employment has affected significant change in how Intel's product development teams approach risk.
Managing Goods and Services Acquisition Risks
There are inherent risks at every stage of the supply chain. In this paper, the authors showcase the employment of three very successful strategies to mitigate the most significant risks at Intel: Internet negotiations, escrow accounts, and currency risk reduction.
Using Forecasting Markets to Manage Demand Risk
The author reviews the threat of demand risk at Intel and the challenge of demand forecasting, describes design considerations for Information Aggregation Mechanisms (IAMs), and explains the excellent results achieved in early experiments at remarkably low cost.
Risk in Daily Business Execution
Risk Management in Restricted Countries
Intel faces numerous challenges when working in or with restricted countries. Our author shows how understanding regulatory requirements and being sensitive to cultural and business differences in these countries has contributed to Intel's ability to build a successful Fab in China, and to make great strides towards working in other countries such as Russia and Vietnam.
Assessment and Control of Environmental, Safety, and Health Risks in Intel's Manufacturing Environment
In this overview paper the authors look at the major environmental, health, and safety risks inherent in semiconductor manufacturing and how early implementation of risk controls helps mitigate down-the-line business losses that occur because of product bans, business interruptions, or even catastrophic events in manufacturing facilities or surrounding communities.
Assessing and Managing Asset Loss from Hazard Risks
Learn how Intel applies a Risk Management Process for hazard risk to mitigate the affects of natural disasters and catastrophic events. The author shows how a disciplined process can identify, control, transfer, and ultimately mitigate the consequences of these risks within semiconductor manufacturing facilities.
Maturation of Business Continuity Practice in the Intel Supply Chain
In order to reliably produce quality products, Intel has to quickly react to a crisis and restore supply to manufacturing and other operations. By employing a business continuity methodology, the authors show how the Materials organization has helped to improve Intel's ability to respond to a crisis.
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Preface
Lin Chao
Publisher
Intel Technology Journal

Technology innovation and technology leadership are not possible for technology companies without a never-ending attention to risk and its management. Using Moore's Law as a roadmap, we, at Intel, need to translate the roadmap into innovative products for the market place and to manage the risk associated with product innovations. This includes both processor microarchitecture innovation and silicon process innovations; both of which go hand in hand. We have developed a model to minimize the risk associated with the introduction of new silicon processes and microarchitectures by alternating our focus. This cadence between microarchitecture and the silicon cycle is referred to as the "tick-tock" model [1]. The term "tick-tock" comes from the steady recurrent ticking sound made by a clock. Each "tick" represents the silicon process beat rate, which has a corresponding "tock" representing the design of a new microarchitecture delivered in a cycle approximately every two years. This model minimizes the risk associated with the introduction of new silicon processes and microarchitectures by alternating the focus from silicon to microarchitecture.

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