Technology and Research
Intel® Technology Journal Home
Volume 10, Issue 02
Intel® Centrino® Duo Processor Technology
Table of Contents
Technical Reviewers
About This Journal
Intel Published Articles
Read Past Journals
Subscribe
E-Mail this Journal to a Collegue
Home  ›  Technology and Research  ›  Intel Technology Journal  ›  Intel® Centrino® Duo Mobile Technology
Main Visual Description
Intel Technology Journal - Featuring Intel's Recent Research and Development
Intel® Centrino® Duo Mobile Technology
Volume 10    Issue 02    Published May 15, 2006
ISSN 1535-864X    DOI: 10.1535/itj.1002.06

  Section 5 of 9  
WLAN System, HW, and RFIC Architecture for the Intel® PRO/Wireless 3945ABG Network Connection
MANUFACTURING TESTING

One of the main bottlenecks in reducing product cost and time to market was the need to significantly reduce production testing time. The new approach described here for the Intel® PRO/Wireless 3945ABG Network Connection enabled a dramatic reduction in test time by a factor of 3 from 104 to 32 seconds per card at the functional testing stage as compared to the previous WLAN product (the Intel® PRO/Wireless 2915ABG Network Connection).

The Wireless HVM process flow involves several stages (see Figure 9), each of which is capable of detecting specific failures.

Structural Test uses X-ray laminography technology, which provides a virtual 3D image "slice" that blurs out all but the selected plane of focus. These 3D cross-section images of solder joints are then evaluated.

Functional Test (FT) station is the first stage where the Intel® PRO/Wireless 3945ABG Network Connection device is inserted into the PC. FT has several goals:

  1. Check for HW failures of the system and sub-components.
  2. Characterize the device’s physical parameters that have an impact on transmit and receive path performance. Tests belonging to this category are called calibration procedures.
  3. EEPROM programming: HW definitions and results of the calibration tests are stored in the device’s EEPROM.

The next stage of the HVM flow is Final Assembly. This is the stage where the wireless device is packed and wrapped with a Label Paper sticker.

The Final Tester is used to verify the programming of the EEPROM, including the MAC address for the device, conduct performance tests on 802.11a/b/g radios, and an association test with an Access Point (AP). After the Final Test is performed, samples of passed units are tested in Ongoing Quality Monitoring (OQM).

The OQM Station runs the same tests as in the Final Tester, but on a defined percentage of the manufactured product. The main requirement of the whole HVM process is that at this station, the Defects Per Million (DPM) level will be below 500 DPM.



Figure 9: Intel® PRO/Wireless 3945ABG Network Connection high-volume manufacturing process flow
click image for larger view
 

Testing time and coverage are a major component of the manufacturing cost and quality of the wireless device, since they have a direct impact on the amount of equipment and testers that is used in the manufacturing line. In order to achieve so dramatic a reduction in testing time relative to our previous wireless products, several approaches were taken:

  1. Working over Product Network Driver (NDIS). Our previous Intel® Wireless LAN products were tested using a specialized version of Validation Driver that was used to directly control the embedded software running on the product board. In the Intel® PRO/Wireless 3945ABG Network Connection project, the role of the network driver was significantly enhanced and most of the features previously handled by the embedded software were moved to the driver level. Therefore, it made sense that the test and validation during FT should also be redone. This ultimately yielded a shorter test time of the product board. For example, the reset test flow through the Network Driver was optimized for speed. Over the Network Driver, it was 10 times faster than testing over an application layer-based test.
  2. Utilizing driver system flows. Additional time savings were achieved by optimizing the time of validation flows. Using the Network Driver also made it possible to take advantage of real WLAN system-flows, such as online DC and TxIQ calibrations, and checking the embedded software image after reset. This enabled us to remove application-layer tests that did not contribute to the test suite coverage.
  3. Using a closed-loop TX power calibration algorithm. By using this we dramatically reduced the amount of required measurement points in the FT tester, as compared to previous projects. This allowed the calibration to be performed in a much shorter time (by a factor of 2.5).
  4. Speeding up the equipment. A special and dedicated effort was made to find the test equipment bottlenecks and to speed up the RF testing equipment used in the FT. Most of the time savings came from speeding up the Power Meter and Spectrum Analyzer equipment data acquisitions.

With regard to test coverage, in our previous projects of wireless HVM testing, there was always doubt as to how close the resemblance was between the driver and the FT software, since they represent two different flows. Using this new approach, this difference was eliminated because the FT was actually running using the same driver as the product, giving us confidence in test quality and reliability. Overall test coverage was increased due to the fact that we were using the Product Network Driver in executing real-life system flows, such as online calibrations, real-time Tx/Rx flows, reset flow, and up-to-date PHY initialization routines. Having the network driver in manufacturing allowed logging of various system parameters across all manufactured boards, which helped us to monitor product health across builds.

Overall, by using the network driver for the Intel® PRO/Wireless 3945ABG Network Connection FT made significant improvements to the Functional Tester Development Program in terms of time and coverage, and this technique will be used in our future Intel® Wi-Fi products.


  Section 5 of 9  

In this article
Abstract
Introduction
Architecture
Design considerations and tradeoffs
Manufacturing testing
Conclusion
Acknowledgments
References
Authors' biographies
Download a PDF of this article.   
Email This Page
Back to Top