System Architecture
The block diagram of the Intel® PRO/Wireless 3945ABG Network Connection is shown in Figure 1. The system is composed of
two chips, fully designed by Intel, and other third-party board components. One chip contains all the digital and
mixed signal components including analog to digital converter (ADC) and digital to analog converter (DAC) while the other
contains the RF sections. The media access control/baseband (MAC/BB) chip consists of the host interface, MAC processor, BB
subsystem (OFDM and CCK modem), and the ADC/DAC. The RFIC chip consists of the synthesizer and full transmit/receive
(TX/RX) chains, from BB to RF.
Figure 1: System block diagram of the Intel® PRO/Wireless 3945ABG Network Connection
click image for larger view
Board Architecture
The board architecture shown in Figure 2 was based on the silicon partitioning and so we had four main sections:
- The MAC/BB with an associated EEPROM (non-volatile memory) used to store all board-specific information
(MAC address, calibration data, regulatory skew information, etc.). The MAC/BB is also the only section that directly
interfaces with the platform through the PCI Express* Mini Card interface.
- The RFIC with an associated Xtal device used to generate all on-board frequencies and clock signals.
- A bias network to enable bias selection, voltage regulation, and power management needed by the system.
- An RF Front End (FE) section comprises antenna and transmit/receive switches, power amplifiers, low-noise
amplifiers, and filtering devices.
Figure 2: Block diagram of the board architecture
click image for larger view
RFIC Architecture
The Si radio chip was designed using 0.18 um CMOS. The floorplan of the radio was designed together with the front end
module (FEM) and package to minimize the spatial mismatch between the chip I/Os with the elements on the board. The
architecture of the radio is shown in Figure 3 and is subdivided into six blocks: synthesizer, logic, RX BB, RX RF, TX BB,
and TX/RF blocks. The logic section receives instructions from the MAC chip to set the system state. The instructions are
then processed and output to the different blocks. The synthesizer is driven by an external clock. The loop basically can
switch between two states to provide the LO signal for the low-band 802.11b/g (2.4-2.5 GHz) and the high-band
802.11a (4.9-5.95 GHz) up/down converters in the TX/RX chains. The dual-band RX chain consists of two
separate RX architectures at the high- and low-bands, respectively. Note that the noise figure of the off-chip
low noise amplifier (LNA) on board fixes the overall RX chain noise figure. A saturation detector at the input to the
down converter is used to detect the power level in the receiver and if the power is too high, the attenuator at the input
of the RX chain is triggered. The I/Q (in-phase and quadrature) signals from the down converter then pass into the BB
section consisting of automatic gain control and active filters. The active filters will provide the out-of-band
signal rejection depending on the system mode (CCK versus OFDM, etc.). The I/Q outputs from the BB section are passed
off-chip via the board to the MAC chip.
Figure 3: Block diagram of the RFIC architecture
click image for larger view
On the TX side, the I/Q data signals from the MAC chip enter the radio chip via the TX BB section where they are
filtered depending on the Wi-Fi standard needed, amplified via the digital gain control amplifier, and then
upconverted to RF. The RF TX section consists of a high pass filter to reduce unwanted spurs at the lower bands followed by
gain controlled amplifiers and a driver amplifier to the off-chip power amplifier (PA). A calibration detector at the
input of the driver stage is used for calibrating the I/Q imbalance in the system.
Front End (FE) Architecture
The FE architecture shown in Figure 4 was basically defined at the system level which then drove the actual FE
component content and requirements. The architecture chosen was a TX/RX architecture where the like TX and RX sections were
all bundled together. This architecture also bundled similar technologies together according to the subgroups. For example,
the PAs are of the same pseudomorphic high electron mobility transistor (PHEMT) GaAs technology, and the LNAs are of the
same heterojunction bipolar transistor (HBT) GaAs technology. The filter passives are of a third technology and typically
integrated in low temperature cofired ceramic (LTCC) technology. Therefore, the FE was subdivided into four category types:
a) dual PA, b) dual LNA, c) switch-diplexer module, and d) balun filters. This "bundling" scheme ultimately created an
industry trend of dual PA and LNA components appearing on the market place.
Figure 4: Front End architecture
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