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Intel® Centrino® Duo Processor Technology
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Home  ›  Technology and Research  ›  Intel Technology Journal  ›  Intel® Centrino® Duo Mobile Technology
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Intel Technology Journal - Featuring Intel's Recent Research and Development
Intel® Centrino® Duo Mobile Technology
Volume 10    Issue 02    Published May 15, 2006
ISSN 1535-864X    DOI: 10.1535/itj.1002.06

  Section 2 of 9  
WLAN System, HW, and RFIC Architecture for the Intel® PRO/Wireless 3945ABG Network Connection
INTRODUCTION

The corporate challenge of being "one generation ahead" in our WLAN product line has challenged us to improve our time to market, product size, and cost. To achieve these goals, we take a top-down approach to our Si and hardware designs in order to optimize platform development. This top-down approach led us to consider the product-level requirements down to the last component on the board, which not only enabled smoother platform integration, but also cheaper products. In this paper, we describe the overall approach used in the development of the Intel® PRO/Wireless 3945ABG Network Connection, which is part of Intel® Centrino® Duo mobile technology, and is the first Intel WLAN product to be conceived using this new top-down approach.

The Intel® PRO/Wireless 3945ABG Network Connection conforms to the IEEE 802.11a/b/g/d/e/h/i standards and supports data rates from 1 Mbps up to 54 Mbps. It is capable of transmitting output powers up to 18 dBm. It operates in the 2.400-2.484 GHz and 5.17-5.85 GHz frequency ranges and supports a Wake on Wireless LAN (WoWLAN) feature.

In this paper we summarize the different architectural/functional design approaches and tradeoffs taken from the system level down to the board and transistor level on Si. First, we summarize the system, board, RFIC, and front-end module architectures. Next, we discuss the design considerations and tradeoffs for each of the architectures. Finally, we summarize the high-volume testing challenges that had to be overcome to enable a reduction in production test time by a factor of 3, from 104 to 32 seconds per card for the wireless platform. The salient features and successes of this overall methodology can be seen in a reduction in the platform integration cycle time from 6 to 4 quarters, a "world class" wireless solution yield improvement through self calibration schemes to better than 98.5%, a modularity approach with built-in reliability checks to the RFIC design flow, migration to a smaller form factor (FF) platform solution (single-sided Mini card) with the lowest part count for this FF class, and a lower product cost achieved through customized board elements and vendor multisourcing.


  Section 2 of 9  

In this article
Abstract
Introduction
Architecture
Design considerations and tradeoffs
Manufacturing testing
Conclusion
Acknowledgments
References
Authors' biographies
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